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CY2037 Datasheet(PDF) 2 Page - Cypress Semiconductor

Part No. CY2037
Description  High Accuracy EPROM Programmable PLL Die for Crystal Oscillators
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com

CY2037 Datasheet(HTML) 2 Page - Cypress Semiconductor

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Functional Description
The CY2037 is an EPROM programmable, high accuracy,
PLL-based die designed for the crystal oscillator market. The
die attaches directly to a low-cost 10-30MHz crystal and can
be packaged into 4-pin through-hole or surface mount pack-
ages. The oscillator devices can be stocked as blank parts and
custom frequencies programmed in-package at the last stage
before shipping. This enables fast-turn manufacture of custom
and standard crystal oscillators without the need for dedicated,
expensive crystals.
The CY2037 contains an on-chip oscillator and a unique oscil-
lator tuning circuit for fine-tuning of the output frequency. The
crystal Cload can be selectively adjusted by programming a set
of seven EPROM bits. This feature can be used to compen-
sate for crystal variations or to obtain a more accurate synthe-
sized frequency.
The CY2037 uses EPROM programming with a simple 2-wire,
4-pin interface that includes VSS and VDD. Clock outputs can
be generated up to 200 MHz at 5V or up to 100 MHz at 3.3V.
The entire configuration can be reprogrammed one time allow-
ing programmed inventory to be altered or reused.
The CY2037 PLL die has been designed for very high resolu-
tion. It has a 12 bit feedback counter multiplier and a 10 bit
reference counter divider. This enables the synthesis of highly
accurate and stable output clock frequencies with zero or low
PPM. The clock can be further modified by eight output divider
options of 1, 2, 4, 8, 16, 32, 64 and 128. The divider input can
be selected as either the PLL or crystal oscillator output pro-
viding a total of sixteen separate output options. For further
flexibility, the ouput is selectable between TTL and CMOS duty
cycle levels.
The CY2037 also contains flexible power management con-
trol. The part includes both PWR_DWN and OE features with
integrated pull-up resistors. The PWR_DWN and OE modes
have an additional setting to determine timing (asynchronous
or synchronous) with respect to the output signal.
Controlled rise and fall times, unique output driver circuits, and
innovative circuit layout techniques enable the CY2037 to
have low jitter and accurate outputs making it suitable for most
PC, networking and consumer applications
EPROM Configuration Block
The following table summarizes the features which are config-
urable by EPROM. Please refer to the “CY2037 Programming
Specification” for further details. The specification can be ob-
tained from your local Cypress representative.
PLL Output Frequency
The CY2037 contains a high resolution PLL with 12 bit multi-
plier and 10 bit divider.The output frequency of the PLL is de-
termined by the following formula:
where P is the feedback counter value and Q is the reference
counter value. P and Q are EPROM programmable values.
Power Management features
The CY2037 contains EPROM programmable PWR_DWN
and OE functions. If Powerdown is selected, all active circuitry
on the chip is shut down when the control pin goes low. The
output is forced to a hard low in this mode and the oscillator
and PLL circuits must re-lock when the part leaves the Power-
down mode. If Output Enable mode is selected, the output is
three-stated when the Control pin goes low. In this mode the
oscillator and PLL circuits continue to operate, allowing a rapid
return to normal operation when the Control input is
In addition, the PWR_DWN and OE modes can be pro-
grammed to occur synchronously or asynchronously with re-
spect to the output signal. When the asynchronous setting is
used, the powerdown or output three-state occurs immediately
(allowing for logic delays) irrespective of position in the clock
cycle. However, when the synchronous setting is used, the
part waits for a falling edge at the output before powerdown or
output enable is initiated, thus preventing output glitches.
Crystal Oscillator Tuning Circuit
The CY2037 contains a unique tuning circuit to fine-tune the
output frequency of the device. The tuning circuit consists of
an array of seven load capacitors on the input side of the os-
cillator drive inverter. The capacitor load values are EPROM
programmable and can be increased in small increments. As
the capacitor load is increased the circuit is fine-tuned to a
lower frequency. The capacitor load values vary from 0.17pF
to 8 pF for a 100:1 total control ratio. The tuning increments
are shown in the table below
Table 1. Crystal Tuning Increments
EPROM Adjustable Features
Feedback counter value (P)
Reference counter value (Q)
Output divider selection
Oscillator Tuning (load capacitance values)
Duty cycle levels (TTL or CMOS)
Power management mode (OE or PWR_DWN)
Power management timing
(synchronous or asynchronous)
+8pF +4.2pF +2.2pF +1.2pF +0.6pF +0.3pF +0.17pF

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