Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

CY2037 Datasheet(PDF) 5 Page - Cypress Semiconductor

Part No. CY2037
Description  High Accuracy EPROM Programmable PLL Die for Crystal Oscillators
Download  7 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
Logo 

CY2037 Datasheet(HTML) 5 Page - Cypress Semiconductor

   
Zoom Inzoom in Zoom Outzoom out
 5 / 7 page
background image
CY2037
PRELIMINARY
5
Output Clock Switching Characteristics Over the Operating Range
Symbol
Description
Test Conditions
Min
Typ
Max
Unit
t1w
Output Duty Cycle at
1.4V, VDD = 4.5–5.5V
t1w = t1A ÷ t1B
1–27 MHz, CL <= 50 pF
27–80 MHz, CL <= 15pF
27–125 MHz, CL <= 25pF
125–200 MHz, CL <= 15pF
45
45
40
40
55
55
60
60
%
%
%
%
t1x
Output Duty Cycle at
VDD/2, VDD = 4.5–5.5V
t1x = t1A ÷ t1B
1–66.6 MHz, CL <= 50 pF
66.6–125 MHz, CL <= 25 pF
125–200 MHz, CL <= 15pF
45
40
40
55
60
60
%
%
%
t1y
Output Duty Cycle at
VDD/2, VDD = 3.0–3.6
t1y = t1A ÷ t1B
1–50 MHz, CL <= 30 pF
50–100 MHz, CL <= 15pF
45
40
55
60
%
%
t1z
Output Duty Cycle at
VDD/2, VDD = 2.7–3.6V
t1z = t1A ÷ t1B
1–40 MHz, CL <= 15 pF
40–66.6 MHz, CL <= 15 pF
45
40
55
60
%
%
t2
Output Clock Rise time
Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 50 pF
Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 25 pF
Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF
Between 0.2VDD– 0.8VDD, VDD= 4.5V–5.5V, CL = 50 pF
Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 30 pF
Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 15 pF
Between 0.2VDD– 0.8VDD, VDD= 2.7V–3.6V, CL = 15 pF
1.8
1.2
0.9
3.4
4.0
2.4
4.0
ns
ns
ns
ns
ns
ns
ns
t3
Output Clock Fall time
Between 0.8V–2.0V, VDD = 4.5V–5.5V, CL = 50 pF
Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 25 pF
Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF
Between 0.2VDD– 0.8VDD, VDD= 4.5V-5.5V, CL = 50 pF
Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 30 pF
Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 15 pF
Between 0.2VDD– 0.8VDD, VDD= 2.7V–3.6V, CL = 15 pF
1.8
1.2
0.9
3.4
4.0
2.4
4.0
ns
ns
ns
ns
ns
ns
ns
t4
Start-up time out of
power-down
PWR_DWN or OE pin LOW to HIGH[2]
1
2
ms
t5a
Power Down delay time
(synchronous setting)
PWR_DWN pin HIGH to output LOW
(T=frequency oscillator period)
T/2
T+10
ns
t5b
Power Down delay time
(asynchronous setting)
PWR_DWN pin HIGH to output LOW
10
15
ns
t6
Power Up time
From power on[2]
1
2
ms
t7a
Output disable time
(synchronous setting)
OE pin HIGH to output Hi-Z
(T=frequency oscillator period)
T/2
T+10
ns
t7b
Output disable time
(asynchronous setting)
OE pin HIGH to output Hi-Z
10
15
ns
t8
Output enable time
PWR_DWN or OE pin LOW to HIGH
100
ns
t9
Peak-to-Peak Period
Jitter
VDD= 4.5V–5.5V, Fo > 33 MHz, VCO > 100 MHz
VDD= 3.0V–3.6V, Fo > 33 MHz, VCO >100 MHz
VDD= 3.0V–5.5V, Fo <33 MHz
±50
±75
±100
±100
±125
±250
ps
ps
ps
Note:
2.
Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.


Html Pages

1  2  3  4  5  6  7 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn