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AT49F8011 Datasheet(PDF) 3 Page - ATMEL Corporation

Part No. AT49F8011
Description  8-megabit (512K x 16/ 1M x 8) 5-volt Only Flash Memory
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Maker  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
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AT49F8011 Datasheet(HTML) 3 Page - ATMEL Corporation

 
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AT49F8011(T)
1264D–FLASH–5/03
Block Diagram
Device
Operation
READ: The AT49F8011(T) is accessed like an EPROM. When CE and OE are low and WE is
high, the data stored at the memory location determined by the address pins are asserted on
the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or
standby mode depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table (I/O8 - I/O15 are don't care inputs for
the command codes). The command sequences are written by applying a low pulse on the
WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Standard microprocessor write timings are used. The address locations used in the
command sequences are not affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. When a high level is reasserted on the RESET pin, the device returns to the Read or
Standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET pin any sector can be reprogrammed even if the sector lockout feature
has been enabled (see Sector Programming Lockout Override section).
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
OUTPUT
BUFFER
INPUT
BUFFER
COMMAND
REGISTER
Y-GATING
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
BYTE
RDY/BUSY
VCC
GND
Y-DECODER
X-DECODER
INPUT
BUFFER
ADDRESS
LATCH
I/O0 - I/O15/A-1
A0 - A18
PLANE B
SECTORS
PLANE A SECTORS


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