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ADC08032 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. ADC08032
Description  8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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ADC08032 Datasheet(HTML) 4 Page - National Semiconductor (TI)

 
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Electrical Characteristics (Continued)
The following specifications apply for V
CC =VREF =+5 VDC, and fCLK = 1 MHz unless otherwise specified. Boldface limits
apply for T
A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 8)
(Note 9)
(Limits)
DIGITAL AND DC CHARACTERISTICS
I
OUT
TRI-STATE® Output Current
V
OUT =0V
−3.0
µA (max)
V
OUT =5V
3.0
µA (max)
I
SOURCE
Output Source Current
V
OUT =0V
−6.5
mA (min)
I
SINK
Output Sink Current
V
OUT =VCC
8.0
mA (min)
I
CC
Supply Current
ADC08031, ADC08034,
CS = HIGH
3.0
mA (max)
and ADC08038
ADC08032 (Note 16)
7.0
mA (max)
REFERENCE CHARACTERISTICS
V
REFOUT
Nominal Reference Output
V
REFOUT Option
Available Only on
2.6
V
ADC08034 and
ADC08038
Electrical Characteristics
The following specifications apply for V
CC =VREF =+5 VDC, and tr =tf = 20 ns unless otherwise specified. Boldface limits
apply for T
A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 8)
(Note 9)
(Limits)
f
CLK
Clock Frequency
10
kHz (min)
1
MHz (max)
Clock Duty Cycle
40
% (min)
(Note 14)
60
% (max)
T
C
Conversion Time (Not Including
f
CLK = 1 MHz
8
1/f
CLK (max)
MUX Addressing Time)
8
µs (max)
t
CA
Acquisition Time
1
2
1/f
CLK(max)
t
SELECT
CLK High while CS is High
50
ns
t
SET-UP
CS Falling Edge or Data Input
25
ns (min)
Valid to CLK Rising Edge
t
HOLD
Data Input Valid after CLK
20
ns (min)
Rising Edge
t
pd1,tpd0
CLK Falling Edge to Output
C
L = 100 pF:
Data Valid (Note 15)
Data MSB First
250
ns (max)
Data LSB First
200
ns (max)
t
1H,t0H
TRI-STATE Delay from Rising Edge
C
L = 10 pF, RL =10 kΩ
50
ns
of CS to Data Output and SARS Hi-Z
(see TRI-STATE Test Circuits)
C
L = 100 pF, RL =2 kΩ
180
ns (max)
C
IN
Capacitance of Logic Inputs
5
pF
C
OUT
Capacitance of Logic Outputs
5
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed speci-
fications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance character-
istics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to AGND = DGND = 0 VDC, unless otherwise specified.
Note 4: When the input voltage VIN at any pin exceeds the power supplies (VIN < (AGND or DGND) or VIN > VCC) the current at that pin should be limited to 5 mA.
The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD =(TJMAX −TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For these de-
www.national.com
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