Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

3D7428 Datasheet(PDF) 3 Page - Data Delay Devices, Inc.

Part No. 3D7428
Description  MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE
Download  7 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  DATADELAY [Data Delay Devices, Inc.]
Homepage  http://www.datadelay.com
Logo 

3D7428 Datasheet(HTML) 3 Page - Data Delay Devices, Inc.

   
Zoom Inzoom in Zoom Outzoom out
 3 / 7 page
background image
3D7428
APPLICATION NOTES (CONT’D)
distortion. Exceeding this limit will generally result
in no signal output.
The recommended maximum operating
frequency specification determines the highest
frequency of the delay line input signal for which
the output delay accuracy is guaranteed.
Exceeding this limit (while remaining within the
absolute limit) may cause some delays to shift
with respect to their values at low frequency. The
amount of delay shift will depend on the degree
to which the limit is exceeded.
To guarantee (if possible) the Table 1 delay
accuracy for input frequencies higher than the
recommended maximum frequency, the 3D7428
must be tested at the user operating frequency.
In this case, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Contact the factory for details.
OPERATING PULSE WIDTH
The absolute minimum operating pulse width
(high or low) specification, tabulated in Table 1,
determines the smallest pulse width of the delay
line input signal that can be reproduced, shifted
in time at the device output, with acceptable
pulse width distortion. Exceeding this limit will
generally result in no signal output.
The recommended minimum operating pulse
width (high or low) specification determines the
smallest pulse width of the delay line input signal
for which the output delay accuracy tabulated in
Table 1 is guaranteed. Exceeding this limit (while
remaining within the absolute limit) may cause
some delays to shift with respect to their values
at long pulse width. The amount of delay shift will
depend on the degree to which the limit is
exceeded.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the recommended
minimum operating pulse width, the 3D7428
must be tested at the user operating pulse width.
In this case, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all.
PROGRAMMED DELAY UPDATE
A delay line is a memory device. It stores
information present at the input for a time equal
to the delay setting before presenting it at the
output with minimal distortion. The 3D7428 8-bit
programmable delay line can be represented by
256 serially connected delay elements
(individually addressed by the programming
data), each capable of storing data for a time
equal to the device increment (step time). The
delay line memory property, in conjunction with
the operational requirement of “instantaneously”
connecting the delay element addressed by the
programming data to the output, may inject
spurious information onto the output data stream.
In order to ensure that spurious outputs do not
occur, it is essential that the input signal be idle
(held high or low) for a short duration prior to
updating the programmed delay. This duration is
given by the maximum programmable delay.
Satisfying this requirement allows the delay line
to “clear” itself of spurious edges. When the new
address is loaded, the input signal can begin to
switch (and the new delay will be valid) after a
time given by tPDV or tEDV (see section below).
PROGRAMMING INTERFACE
Figure 1 illustrates the main functional blocks of
the 3D7428 delay program interface. Since the
3D7428 is a CMOS design, all unused input pins
must be returned to well defined logic levels,
VDD or Ground.
TRANSPARENT PARALLEL MODE (MD = 1,
AE = 1)
The eight program pins P0 - P7 directly control
the output delay. A change on one or more of
the program pins will be reflected on the output
delay after a time tPDV, as shown in Figure 2. A
register is required if the programming data is
bused.
Doc #03003
DATA DELAY DEVICES, INC.
3
11/1/04
3 Mt. Prospect Ave. Clifton, NJ 07013


Html Pages

1  2  3  4  5  6  7 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn