SiC461, SiC462, SiC463, SiC464

www.vishay.com

Vishay Siliconix

S18-0393-Rev. K, 16-Apr-18

10

Document Number: 65124

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Pre-Bias Start-Up

In case of pre-bias startup, output is monitored through FB

pin. If the sensed voltage on FB is higher than the internal

reference ramp value, control logic prevents high side and

low side MOSFETs from switching to avoid negative output

voltage spike and excessive current sinking through low

side MOSFET.

Fig. 8 - Pre-Bias Start-Up

Power Good

pin high through a > 10K resistor to use this signal. Power

good window is shown in the below diagram. If voltage on

EXAMPLE SCHEMATIC OF SiC462

Fig. 10 - SiC462 Configured for 6 V to 60 V Input, 5 V Output at 6 A, 500 kHz Operation with Ultrasonic Power Save Mode Enabled

all Ceramic Output Capacitance Design

VFB_Rising_Vth_OV

(typ. = 0.96 V)

VFB_Falling_Vth_OV

(typ. = 0.91 V)

VFB_Falling_Vth_UV

(typ. = 0.72 V)

VFB_Rising_Vth_UV

(typ. = 0.77 V)

PG

Pull-high

Pull-low

SiC462

U1

17

28

1

11

10

9

8

7

COMP

21

22

23

24

25

26

MODE

27

30

29

Notes in small black text near

component values refer to Vishay

SiC46X spreadsheet calcualtor

references.

+V

6 V to 60 V

PG

L

+V

P

GND

Zero ohm ultrasonic select

EN

Analog ground (A

power ground (P

tied internally in the SiC46X

A

GND

A

GND

P

GND

560K

102K

DNP

33 nF

2K

1 μF

60.4K

0.1 μF

52.3K

47 μF

10K

4.7 μF

470 pF

232K

52.3K

128 μF

0.1 μF

4.7 μH

8.66K

2.2 nF

1.8 nF