Document Number: 002-00646 Rev. *M

Page 8 of 45

S25FL128P

6.

SPI Modes

A microcontroller can use either of its two SPI modes to control Cypress SPI Flash memory devices:



CPOL = 0, CPHA = 0 (Mode 0)



CPOL = 1, CPHA = 1 (Mode 3)

Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes.

When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes:



SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)



SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)

Figure 6.1 Bus Master and Memory Devices on the SPI Bus

Note

The Write Protect/Accelerated Programming (WP#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate.

Figure 6.2 SPI Modes Supported

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

Bus Master

CS3

CS2

CS1

SPI Memory

Device

SPI Memory

Device

SPI Memory

Device

CS#

HOLD#

CS#

HOLD#

CS#

WP#/ACC

WP#/ACC

WP#/ACC

HOLD#

SCK SO SI

SCK SO SI

SCK SO SI

SO

SI

SCK

MSB

MSB

SCK

SCK

SI

SO

CPHA

CPOL

00

11

CS#

Mode 0

Mode 3