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ADCMP573 Datasheet(PDF) 1 Page - Analog Devices |
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ADCMP573 Datasheet(HTML) 1 Page - Analog Devices |
1 / 16 page Ultrafast 3.3 V Single-Supply Comparators Preliminary Technical Data ADCMP572/ADCMP573 Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. FEATURES 3.3 V/5.2 V single-supply operation 150 ps propagation delay 15 ps overdrive and slew rate dispersion 8 GHz equivalent input risetime bandwidth 80 ps minimum pulse width 35 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) On-chip terminations at both input pins Robust inputs with no output phase reversal Resistor programmable hysteresis Differential latch control Power supply rejection > 70 dB APPLICATIONS Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration FUNCTIONAL BLOCK DIAGRAM VP NONINVERTING INPUT VTP TERMINATION VTN TERMINATION VN INVERTING INPUT LE INPUT HYS Q OUTPUT Q OUTPUT LE INPUT ADCMP572 ADCMP573 CML/ RSPECL VCCO VCCI Figure 1. GENERAL DESCRIPTION The ADCMP572/ADCMP573 are ultrafast comparators fabricated on Analog Devices, Inc.’s proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP572 features CML output drivers, and the ADCMP573 features reduced swing PECL (RSPECL) output drivers. Both devices offer 150 ps propagation delay and 100 ps minimum pulse width for 10 Gbps operation with 200 fs RMS random jitter (RJ). Overdrive and slew rate dispersion is typically less than 15 ps. A flexible power supply scheme allows either device to operate with a single +3.3 V positive supply and a −0.2 V to +1.2 V input signal range, or with split input/output supplies to support a wider −0.2 V to +3.2 V input signal range and an independent range of output levels. 50 Ω on-chip termination resistors are provided at both inputs with the optional capability to leave open (on an individual pin basis) for applications requiring high impedance inputs. The CML output stage is designed to directly drive 400 mV into 50 Ω transmission lines terminated to between 3.3 V to 5.2 V. The RSPECL output stage is designed to drive 400 mV into 50 Ω terminated to VCCO − 2 V and is compatible with several commonly used PECL logic families. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided. The ADCMP572/ADCMP573 are available in a 16-lead LFCSP package. |
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