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S71PL064JB0-0B Datasheet(PDF) 8 Page - SPANSION |
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S71PL064JB0-0B Datasheet(HTML) 8 Page - SPANSION |
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8 / 196 page  8 S71PL254/127/064/032J_00_A6 November 22, 2004 Advance I n f o rmation MCP Block Diagram Notes: 1. For 1 Flash + pSRAM, CE#f1=CE#. For 2 Flash + pSRAM, CE#=CE#f1 and CE#f2 is the chip-enable for the second Flash. 2. For 256Mb only, Flash 1 = Flash 2 = S29PL127J. VSS RESET# Flash 1 IO15-IO0 VCCf DQ15 to DQ0 RY/BY# WP#/ACC VCC VCC CE#f1 Flash-only Address Shared Address OE# WE# Flash 2 (Note 2) CE#f2 (Note 1) VCCS VCC CE#s UB#s LB#s CE# UB# LB# pSRAM/SRAM CE2 |
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