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S25FL004AOLMFI000 Datasheet(PDF) 3 Page - SPANSION |
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S25FL004AOLMFI000 Datasheet(HTML) 3 Page - SPANSION |
3 / 39 page Publication Number S25FL004A_00 Revision A Amendment 1 Issue Date March 28, 2005 ADVANCE INFORMATION S25FL Family (Serial Peripheral Interface) S25FL004A 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface Data Sheet Distinctive Characteristics Architectural Advantages Single power supply operation — Full voltage range: 2.7 to 3.6 V read and program operations Memory Architecture — Eight sectors with 512 Kb each Program — Page Program (up to 256 bytes) in 1.5 ms (typical) — Program cycles are on a page by page basis Erase — 1.5 s typical sector erase time — 12 s typical bulk erase time Cycling Endurance — 100,000 cycles per sector typical Data Retention — 20 years typical Device ID — JEDEC standard two-byte electronic signature — RES instruction one-byte electronic signature for backward compatibility Process Technology — Manufactured on 0.20 µm MirrorBitTM process technology Package Option — Industry Standard Pinouts — 8-pin SO package (208 mils) — 8-Contact USON Package (5 x 6 mm), Pb-Free Performance Characteristics Speed — 50 MHz clock rate (maximum) Power Saving Standby Mode — Standby Mode 50 µA (max) — Deep Power Down Mode 1 µA (typical) Memory Protection Features Memory Protection — W# pin works in conjunction with Status Register Bits to protect specified memory areas — Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as read- only Software Features SPI Bus Compatible Serial Interface |
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