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S29AL016D Datasheet(PDF) 2 Page - SPANSION

Part No. S29AL016D
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S29AL016D_00_A2 December 17, 2004
Pr e l i m i n a r y
General Description
The S29AL016D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152
bytes or 1,048,576 words. The device is offered in 48-ball FBGA, and 48-pin TSOP
packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8)
data appears on DQ7–DQ0. This device is designed to be programmed in-system
with the standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not
required for write or erase operations. The device can also be programmed in
standard EPROM programmers.
The device offers access times of 70 ns and 90 ns allowing high speed micropro-
cessors to operate without wait states. To eliminate bus contention the device has
separate chip enable (CE#), write enable (WE#) and output enable (OE#)
The device requires only a single 3.0 volt power supply for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations.
The S29AL016D is entirely command set compatible with the JEDEC single-
power-supply Flash standard. Commands are written to the command regis-
ter using standard microprocessor write timings. Register contents serve as input
to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This
initiates the Embedded Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates
the Embedded Erase algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) before executing the erase
operation. During erase, the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by
observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (tog-
gle) status bits. After a program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automat-
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on
hold for any period of time to read data from, or program data to, any sector that
is not selected for erasure. True background erase can thus be achieved.

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