PRELIMINARY
CY7C1370D
CY7C1372D
Document #: 38-05555 Rev. *A
Page 10 of 30
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1370D/CY7C1372D incorporates a serial boundary
scan test access port (TAP). This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3V or
2.5V I/O logic levels.
The CY7C1370D/CY7C1372D contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1370D)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
L
HHH
L
Write Byte b – (DQb and DQPb)L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
LHLH
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Function (CY7C1372D)
WE
BWb
BWa
Read
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)L
H
L
Write Byte b – (DQb and DQPb)L
L
H
Write Both Bytes
L
L
L
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