Electronic Components Datasheet Search
  English  ▼

Delete All


Preview PDF Download HTML

MPC93R51 Datasheet(PDF) 1 Page - Motorola, Inc

Part No. MPC93R51
Download  12 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com

MPC93R51 Datasheet(HTML) 1 Page - Motorola, Inc

Zoom Inzoom in Zoom Outzoom out
 1 / 12 page
background image
Order Number: MPC93R51/D
Rev 0, 12/2002
© Motorola, Inc. 2002
Low Voltage PLL Clock Driver
The MPC93R51 is a 3.3V compatible, PLL based clock generator
targeted for high performance clock distribution systems. With output
frequencies of up to 240 MHz and a maximum output skew of 150 ps the
MPC93R51 is an ideal solution for the most demanding clock tree
designs. The device offers 9 low skew clock outputs, each is configurable
to support the clocking needs of the various high-performance
microprocessors including the PowerQuicc II integrated communication
microprocessor. The devices employs a fully differential PLL design to
minimize cycle-to-cycle and long-term jitter.
9 outputs LVCMOS PLL clock generator
25 - 240 MHz output frequency range
Fully integrated PLL
Compatible to various microprocessors such as PowerQuicc II
Supports networking, telecommunications and computer applications
Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
LVPECL and LVCMOS compatible inputs
External feedback enables zero-delay configurations
Output enable/disable and static test mode (PLL enable/disable)
Low skew characteristics: maximum 150 ps output-to-output
Cycle-to-cycle jitter max. 22 ps RMS
32 lead LQFP package
Ambient Temperature Range 0°C to +70°C
Pin & Function Compatible with the MPC951
Functional Description
The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal
operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback
path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be
selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8 the internal VCO of the
MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is
either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the
FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and
1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK).
The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the
selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system
diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply.
The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose
lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also
enabling the PLL to recover to normal operation. The MPC93R51 is 3.3V compatible and requires no external loop filter
components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels
with the capability to drive terminated 50
W transmission lines. For series terminated transmission lines, each of the MPC93R51
outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm2 32-lead
LQFP package.
Application Information
The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with
essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase
offset between the outputs and the reference signal.
CASE 873A–02
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12 

Datasheet Download

Related Electronics Part Number

Part NumberComponents DescriptionHtml ViewManufacturer
MPC932LOW VOLTAGE PLL CLOCK DRIVER 1 2 3 4 5 MoreMotorola, Inc
MPC990LOW VOLTAGE PLL CLOCK DRIVER 1 2 3 4 5 MoreMotorola, Inc
PI6C2972Low Voltage PLL Clock Driver 1 2 3 4 5 MorePericom Semiconductor Corporation
MPC992LOW VOLTAGE PLL CLOCK DRIVER 1 2 3 4 5 MoreMotorola, Inc
IDT5V9351LOW VOLTAGE PLL CLOCK DRIVER 1 2 3 4 5 MoreIntegrated Device Technology
MPC958LOW VOLTAGE PLL CLOCK DRIVER 1 2 3 4 5 MoreMotorola, Inc
PI6C2952Low Voltage PLL Clock Driver 1 2 3 4 5 MorePericom Semiconductor Corporation
MPC950LOW VOLTAGE PLL CLOCK DRIVER 1 2 3 4 5 MoreMotorola, Inc
MPC9350LOW VOLTAGE PLL CLOCK DRIVER 1 2 3 4 5 MoreMotorola, Inc
MPC952LOW VOLTAGE PLL CLOCK DRIVER 1 2 3 4 5 MoreMotorola, Inc

Link URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com

Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn