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M54977P Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor

Part No. M54977P
Description  Bi-CMOS 12-BIT SERIAL-INPUT LATCHED DRIVER
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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M54977P Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor

   
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Bi-CMOS 12-BIT SERIAL-INPUT LATCHED DRIVER
M54977P
MITSUBISHI <CONTROL / DRIVER IC>
20
17
18
19
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4
3
2
16
5
15
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14
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13
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12
9
11
10
DESCRIPTION
The M54977P is a semiconductor integrated circuit fabricated
using Bi-CMOS technology. It contains a
serial input to
serial/parallel output 12-bit CMOS shift register and CMOS latch as
well as bipolar 12-bit parallel-output driver.
FEATURES
q Serial input to serial/parallel output
q Cascade connections possible through serial output
q Latch circuit included for each stage
q Enable input for output control
q Low supply current .................................. ICC
≥ 10µA at standby
q Serial input/output level is compatible with standard CMOS
q Driver : Withstand voltage ...................................... BVCEO
≥ 30V
Large drive current ................................ (IO(max)=200mA)
q Wide operating temperature range ..................... Ta=-20 – +75
°C
APPLICATION
Thermal printer head dot driver, Serial-to parallel conversion,
Relay, solenoid driver
FUNCTION
The M54977P consists of an 12-bit D-type flip-flop, the output of
which is connected to 12 latches.
When data is applied to the serial data input (S-IN) and a clock
pulse is applied to clock input (T), an “L” to “H” change of the clock
will cause the data input signals to enter the internal shift registers
and the data in the shift registers will be shifted in order.
Using a number of M54977P units for bit expansion in series will
entail connecting serial output (S-OUT) to S-IN of the next-stage
M54977P.
In parallel output, when the latch input is set to “H” and the output-
control input (enable input EN) is “L”, a clock pulse changing from
“L” to “H” will cause the serial data input signal to appear at output
O1, and the data will be shifted in order at outputs O2 – O12.
The parallel output will yield a signal that is inverted with respect to
the serial data input.
BLOCK DIAGRAM
PIN CONFIGURATION (TOP VIEW)
T
S-IN
L-GND
VCC
S-OUT
LATCH
EN
P-GND
O1
O2
O3
O4
O5
O6
O7
O8
Clock
Serial input
Logic GND
Serial output
Latch input
Enable input
Driver GND
Parallel outputs
Outline 20P4
O9
O10
O12
O11
Parallel outputs
Q
L D
O1
Clock T
Q
T
D
Q
L D
O2
Q
T
D
Q
L D
O3
Q
T
D
Q
L D
O4
Q
T
D
Q
L D
O5
Q
T
D
Q
L D
O6
Q
T
D
Q
L D
O7
Q
T
D
Q
L D
O8
Q
T
D
Q
L D
O9
Q
T
D
Q
L D
O10
Q
T
D
Q
L D
O11
Q
T
D
Q
L D
O12
Q
T
D
EN
S-OUT
Serial output
P-GND
Driver GND
Parallel outputs
Power supply VCC
Latch input
LATCH
Serial input
S-IN
Enable input
3
1
2
6
4
7
10
5
20
19
18
17
16
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11
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8
L-GND


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