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CY2077
Document #: 38-07210 Rev. *B
Page 8 of 13
Note:
8.
Rise/Fall Time for CMOS output is measured between 1.2 VDD and 0.8 VDD. Rise/Fall Time for TTL output is measured between 0.8V and 2.0V.
Rise/Fall Time vs. VDD over Temperatures
Rise/Fall Time vs. Output Loads over Temperatures
Rise Time vs. VDD -- CMOS duty Cycle
Cload = 15pF
1.00
1.20
1.40
1.60
1.80
2.00
2.7
3.0
3.3
3.6
3.9
VDD (V)
-40C
25C
85C
Fall Time vs. VDD -- CMOS duty Cycle
Cload = 15pF
1.00
1.20
1.40
1.60
1.80
2.00
2.7
3.0
3.3
3.6
3.9
VDD (V)
-40C
25C
85C
Rise Time vs. VDD -- TTL duty Cycle
Cload = 15pF
0.20
0.30
0.40
0.50
0.60
0.70
4.0
4.5
5.0
5.5
6.0
VDD (V)
-40C
25C
85C
Fall Time vs. VDD -- TTL duty Cycle
Cload = 15pF
0.20
0.30
0.40
0.50
0.60
0.70
4.0
4.5
5.0
5.5
6.0
VDD (V)
-40C
25C
85C
Rise Time vs. CLoad over Temperature
VDD = 3.3v, CMOS output
1.00
1.50
2.00
2.50
10
15
20
25
30
35
Cload (pF)
-40C
25C
85C
Fall Time vs. CLoad over Temperature
VDD = 3.3v, CMOS output
1.00
1.50
2.00
10
15
20
25
30
35
Cload (pF)
-40C
25C
85C
Typical Rise Time
[8] and Fall Time[8] Trends for CY2077
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