32K/64K x16/18
Synchronous Dual Port Static RAM
CY7C09279/89
CY7C09379/89
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06040 Rev. **
Revised September 19, 2001
25/0251
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• Six Flow-Through/Pipelined devices
— 32K x 16/18 organization (CY7C09279/379)
— 64K x 16/18 organization (CY7C09289/389)
• Three Modes
— Flow-Through
— Pipelined
—Burst
• Pipelined output mode on both ports allows fast 100-
MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5[1]/7.5/9/12 ns
(max.)
• Low operating power
— Active = 195 mA (typical)
— Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to IDT70927
and IDT709279
Notes:
1.
See page 6 for Load Conditions.
2.
I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
3.
I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.
4.
A0–A14 for 32K; A0–A15 for 64K devices.
Logic Block Diagram
R/WL
1
0
0/1
CE0L
CE1L
LBL
OEL
UBL
1b
0/1
0b 1a 0a
ba
FT/PipeL
I/O8/9L–I/O15/17L
I/O0L–I/O7/8L
I/O
Control
Counter/
Address
Register
Decode
A0L–A14/15L
CLKL
ADSL
CNTENL
CNTRSTL
True Dual-Ported
RAM Array
R/WR
1
0
0/1
CE0R
CE1R
LBR
OER
UBR
1b
0/1
0b
1a
0a
b
a
FT/PipeR
I/O
Control
Counter/
Address
Register
Decode
15/16
8/9
8/9
I/O8/9R–I/O15/17R
I/O0R–I/O7/8R
A0R–A14/15R
CLKR
ADSR
CNTENR
CNTRSTR
15/16
8/9
8/9
[2]
[3]
[2]
[3]
[4]
[4]
For the most recent information, visit the Cypress web site at www.cypress.com