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AM29DS163DB100WAKN Datasheet(PDF) 11 Page - Advanced Micro Devices |
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AM29DS163DB100WAKN Datasheet(HTML) 11 Page - Advanced Micro Devices |
11 / 50 page Am29DS163D 11 ADV ANCE I N FO RMAT I O N addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” on page 10 for more information. Refer to the Table on page 36 for timing specifications and to Figure 13, on page 36 for the timing diagram. ICC1 in the DC Charac- t e ri s tic s ta bl e r e p r es en ts t h e a c t i v e c u r r e n t specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” on page 10 for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Configuration” section contains details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 3 on page 13 to Table 6 on page 14 indicate the address space that each sector occupies. The device address space is di- v i ded into t w o bank s : Bank 1 c ont ains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits re- quired to uniquely select a sector. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The “AC Characteristics” on page 36 section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated program- ming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to “Autoselect Mode” on page 15 and “Autoselect Command Sequence” on page 23 for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 20, on page 42 shows how read and write cycles may be initiated for simultaneous opera- tion with zero latency. ICC6 and ICC7 in the DC Characteristics table represent the current specifica- tions for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires stan- dard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. |
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