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CY7C1307BV25-133BZC Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C1307BV25-133BZC
Description  18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1307BV25-133BZC Datasheet(HTML) 8 Page - Cypress Semiconductor

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PRELIMINARY
CY7C1305BV25
CY7C1307BV25
Document #: 38-05630 Rev. **
Page 8 of 21
Write Cycle Descriptions (CY7C1307BV25)[2, 10]
BWS0
BWS1
BWS2
BWS3
KK
Comments
L
L
L
L
L-H
During the Data portion of a Write sequence, all four bytes
(D[35:0]) are written into the device.
L
L
L
L
L-H
During the Data portion of a Write sequence, all four bytes
(D[35:0]) are written into the device.
L
H
H
H
L-H
During the Data portion of a Write sequence, only the lower
byte (D[8:0]) is written into the device. D[35:9] will remain
unaltered.
L
H
H
H
L-H
During the Data portion of a Write sequence, only the lower
byte (D[8:0]) is written into the device. D[35:9] will remain
unaltered.
H
L
H
H
L-H
During the Data portion of a Write sequence, only the byte
(D[17:9]) is written into the device. D[8:0] and D[35:18] will
remain unaltered.
H
L
H
H
L-H
During the Data portion of a Write sequence, only the byte
(D[17:9]) is written into the device. D[8:0] and D[35:18] will
remain unaltered.
H
H
L
H
L-H
During the Data portion of a Write sequence, only the byte
(D[26:18]) is written into the device. D[17:0] and D[35:27] will
remain unaltered.
H
H
L
H
L-H
During the Data portion of a Write sequence, only the byte
(D[26:18]) is written into the device. D[17:0] and D[35:27] will
remain unaltered.
H
H
H
L
L-H
During the Data portion of a Write sequence, only the byte
(D[35:27]) is written into the device. D[26:0] will remain
unaltered.
H
H
H
L
L-H
During the Data portion of a Write sequence, only the byte
(D[35:27]) is written into the device. D[26:0] will remain
unaltered.
H
H
H
H
L-H
No data is written into the device during this portion of a Write
operation.
H
H
H
H
L-H
No data is written into the device during this portion of a write
operation.
Note:
10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0 and BWS1 in the case of CY7C1305BV25 and BWS2 and BWS3 in
the case of CY7C1307BV25 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.


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