CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A
Page 8 of 19
Data Retention Mode
The CY7C027/028 and CY7C037/038 are designed with bat-
tery backup in mind. Data retention voltage and supply current
are guaranteed over temperature. The following rules ensure
data retention:
1. Chip enable (CE) must be held HIGH during data retention, with-
in VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 volts).
BUSY TIMING[20]
tBLA
BUSY LOW from Address Match
12
15
20
ns
tBHA
BUSY HIGH from Address Mismatch
12
15
20
ns
tBLC
BUSY LOW from CE LOW
12
15
20
ns
tBHC
BUSY HIGH from CE HIGH
12
15
17
ns
tPS
Port Set-Up for Priority
5
5
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
11
13
15
ns
tBDD
[21]
BUSY HIGH to Data Valid
12
15
20
ns
INTERRUPT TIMING[20]
tINS
INT Set Time
12
15
20
ns
tINR
INT Reset Time
12
15
20
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE or SEM)
10
10
10
ns
tSWRD
SEM Flag Write to Read Time
5
5
5
ns
tSPS
SEM Flag Contention Window
5
5
5
ns
tSAA
SEM Address Access Time
12
15
20
ns
Switching Characteristics Over the Operating Range[14] (continued)
Parameter
Description
CY7C027/028
CY7C037/038
Unit
-12[1]
-15
-20
Min.
Max.
Min.
Max.
Min.
Max.
Timing
Parameter
Test Conditions[22]
Max.
Unit
ICCDR1
@ VCCDR = 2V
1.5
mA
Data Retention Mode
4.5V
4.5V
VCC > 2.0V
VCC to VCC – 0.2V
VCC
CE
tRC
V
IH
Notes:
20. Test conditions used are Load 1.
21. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
22. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
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