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FM31L276-G Datasheet(PDF) 23 Page - Cypress Semiconductor |
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FM31L276-G Datasheet(HTML) 23 Page - Cypress Semiconductor |
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23 / 36 page  FM31L276/FM31L278 Document Number: 001-86392 Rev. *C Page 23 of 36 Addressing Overview - Memory After the FM31L276/FM31L278 (as receiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. The address requires two bytes. The complete 15-bit address is latched internally. Each access causes the latched address value to be incremented automati- cally. The current address is the value that is held in the latch; either a newly written value or the address following the last access. The current address will be held for as long as VDD >VTP or until a new value is written. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below. After transmission of each data byte, just prior to the acknowledge, the FM31L276/FM31L278 increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing. After the last address (7FFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. Addressing Overview - RTC & Companion The RTC and Processor Companion operate in a similar manner to the memory, except that it uses only one byte of address. Addresses 00h to 18h correspond to special function registers. Attempting to load addresses above 18h is an illegal condition; the FM31L276/FM31L278 will return a NACK and abort the I2C transaction. Data Transfer After the address bytes have been transmitted, data transfer between the bus master and the FM31L276/FM31L278 can begin. For a read operation the FM31L276/FM31L278 will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM31L276/FM31L278 will transfer the next sequential byte. If the acknowledge is not sent, the FM31L276/FM31L278 will end the read operation. For a write operation, the FM31L276/FM31L278 will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first. |
Similar Part No. - FM31L276-G |
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Similar Description - FM31L276-G |
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