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FM31L276-G Datasheet(PDF) 31 Page - Cypress Semiconductor |
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FM31L276-G Datasheet(HTML) 31 Page - Cypress Semiconductor |
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31 / 36 page  FM31L276/FM31L278 Document Number: 001-86392 Rev. *C Page 31 of 36 AC Switching Characteristics Over the Operating Range Parameter[12] Description Min Max Min Max Min Max Unit Cypress Parameter Alt. Parameter fSCL SCL clock frequency 0 100 0 400 0 1000 kHz tSU; STA Start condition setup for repeated Start 4.7 – 0.6 – 0.25 – s tHD;STA Start condition hold time 4.0 – 0.6 – 0.25 – s tLOW Clock LOW period 4.7 – 1.3 – 0.6 – s tHIGH Clock HIGH period 4.0 – 0.6 – 0.4 – s tSU;DAT tSU;DATA Data in setup 250 – 100 – 100 – ns tHD;DAT tHD;DATA Data in hold 0 – 0 – 0 – ns tDH Data output hold (from SCL @ VIL) 0 – 0 – 0 – ns tR[13] tr Input rise time – 1000 – 300 – 300 ns tF[13] tf Input fall time – 300 – 300 – 100 ns tSU;STO STOP condition setup 4 – 0.6 0.25 – s tAA tVD;DATA SCL LOW to SDA Data Out Valid – 3 – 0.9 – 0.55 s tBUF Bus free before new transmission 4.7 – 1.3 – 0.5 – s tSP Noise suppression time constant on SCL, SDA – 50 – 50 – 50 ns Figure 25. Read Bus Timing Diagram Figure 26. Write Bus Timing Diagram tSU:SDA Start tR ` tF Stop Start tBUF tHIGH 1/fSCL tLOW tSP tSP Acknowledge tHD:DAT tSU:DAT tAA tDH SCL SDA tSU:STO Start Stop Start Acknowledge tAA tHD:DAT tHD:STA tSU:DAT SCL SDA Notes 12. Test conditions assume a signal transition time of 10 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 100 pF load capacitance shown in Figure 23 on page 29. 13. This parameter is characterized and not 100% tested. |
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