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FM28V202A-TGTR Datasheet(PDF) 11 Page - Cypress Semiconductor |
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FM28V202A-TGTR Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 22 page  FM28V202A Document Number: 001-90309 Rev. *G Page 11 of 22 AC Switching Characteristics Over the Operating Range Parameters [3] Description VDD = 2.0 V to 2.7 V VDD = 2.7 V to 3.6 V Unit Cypress Parameter Alt Parameter Min Max Min Max SRAM Read Cycle tCE tACE Chip enable access time – 70 – 60 ns tRC – Read cycle time 105 – 90 ns tAA – Address access time, A16-2 –105 – 90 ns tOH tOHA Output hold time, A16-2 20 – 20 – ns tAAP – Page mode access time, A1-0 –40 – 30 ns tOHP – Page mode output hold time, A1-0 3– 3 – ns tCA – Chip enable active time 70 – 60 – ns tPC – Pre-charge time 35 – 30 – ns tBA tBW UB, LB access time – 25 – 15 ns tAS tSA Address setup time (to CE LOW) 0– 0 – ns tAH tHA Address hold time (CE Controlled) 70 – 60 – ns tOE tDOE Output enable access time – 25 – 15 ns tHZ[4, 5] tHZCE Chip Enable to output HI-Z – 15 – 10 ns tOHZ[4, 5] tHZOE Output enable HIGH to output HI-Z – 15 – 10 ns tBHZ[4, 5] tHZBE UB, LB HIGHHIGH to output HI-Z – 15 – 10 ns Notes 3. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified IOL/IOH and 30-pF load capacitance shown in AC Test Conditions on page 10. 4. tHZ, tOHZ and tBHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 5. This parameter is characterized but not 100% tested. |
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