FM16W08

Document Number: 001-86210 Rev. *F

Page 10 of 18

SRAM Write Cycle

Write cycle time

145

–

130

–

ns

–

Chip enable active time

80

–

70

–

ns

Chip enable to write enable HIGH

80

–

70

–

ns

–

Pre-charge time

65

–

60

–

ns

Write enable pulse width

50

–

40

–

ns

Address setup time

0–0–

ns

Address hold time

15

–

15

–

ns

Data input setup time

40

–

30

–

ns

Data input hold time

0–0–

ns

Write enable LOW to output HI-Z

–

15

–

15

ns

–

Write enable HIGH to output driven

10

–

10

–

ns

–

Chip enable to output HI-Z

–

15

–

15

ns

–

Write enable to CE LOW setup time

0

–

0

–

ns

–

Write enable to CE HIGH hold time

0

–

0

–

ns

Description

Unit

Cypress

Parameter

Alt Parameter

Min

Max

Min

Max

Notes

6. This parameter is characterized but not 100% tested.

7. The relationship between CE and WE determines if a CE or WE controlled write occurs.