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FM16W08 Datasheet(PDF) 10 Page - Cypress Semiconductor |
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FM16W08 Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 18 page FM16W08 Document Number: 001-86210 Rev. *F Page 10 of 18 SRAM Write Cycle tWC tWC Write cycle time 145 – 130 – ns tCA – Chip enable active time 80 – 70 – ns tCW tSCE Chip enable to write enable HIGH 80 – 70 – ns tPC – Pre-charge time 65 – 60 – ns tWP tPWE Write enable pulse width 50 – 40 – ns tAS tSA Address setup time 0–0– ns tAH tHA Address hold time 15 – 15 – ns tDS tSD Data input setup time 40 – 30 – ns tDH tHD Data input hold time 0–0– ns tWZ[5, 6] tHZWE Write enable LOW to output HI-Z – 15 – 15 ns tWX[6] – Write enable HIGH to output driven 10 – 10 – ns tHZ[5] – Chip enable to output HI-Z – 15 – 15 ns tWS[7] – Write enable to CE LOW setup time 0 – 0 – ns tWH[7] – Write enable to CE HIGH hold time 0 – 0 – ns AC Switching Characteristics (continued) Over the Operating Range Parameters [2] Description VDD = 2.7 V to 3.0 V VDD = 3.0 V to 5.5 V Unit Cypress Parameter Alt Parameter Min Max Min Max Notes 5. tWZ and tHZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 6. This parameter is characterized but not 100% tested. 7. The relationship between CE and WE determines if a CE or WE controlled write occurs. |
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