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CY62168G30-45BVXIT Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY62168G30-45BVXIT Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 19 page Document Number: 001-84771 Rev. *I Page 9 of 19 CY62168G/CY62168GE MoBL® Switching Characteristics Parameter [18, 19] Description 45 ns 55 ns Unit Min Max Min Max Read Cycle tRC Read cycle time 45.0 – 55.0 – ns tAA Address to data valid / Address to ERR valid – 45.0 – 55.0 ns tOHA Data hold from address change / ERR hold from address change 10.0 – 10.0 – ns tACE CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR valid – 45.0 – 55.0 ns tDOE OE LOW to data valid / OE LOW to ERR valid – 22.0 – 25.0 ns tLZOE OE LOW to Low Z [19, 20] 5.0 – 5.0 – ns tHZOE OE HIGH to High Z [19, 20, 21] – 18.0 – 18.0 ns tLZCE CE1 LOW and CE2 HIGH to Low Z [19, 20] 10.0 – 10.0 – ns tHZCE CE1 HIGH and CE2 LOW to High Z [19, 20, 21] – 18.0 – 18.0 ns tPU [22] CE1 LOW and CE2 HIGH to power-up 0 – 0 – ns tPD [22] CE1 HIGH and CE2 LOW to power-down – 45.0 – 55.0 ns Write Cycle[23, 24] tWC Write cycle time 45.0 – 55.0 – ns tSCE CE1 LOW and CE2 HIGH to write end 35.0 – 40.0 – ns tAW Address setup to write end 35.0 – 40.0 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 35.0 – 40.0 – ns tSD Data setup to write end 25.0 – 25.0 – ns tHD Data hold from write end 0 – 0 – ns tHZWE WE LOW to High Z [19, 21, 20] – 18.0 – 20.0 ns tLZWE WE HIGH to Low Z [19, 20] 10.0 – 10.0 – ns Notes 18. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless specified otherwise. 19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 20. Tested initially and after any design or process changes that may affect these parameters. 21. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 22. These parameters are guaranteed by design and are not tested. 23. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 24. The minimum write cycle pulse width for write cycle No. 2 (WE Controlled, OE Low) should be equal to he sum of tHZWE and tSD. |
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