VITESSE

SEMICONDUCTOR CORPORATION

®

Advance Product Information

VSC7182

Quad Transceiver

for Gigabit Ethernet and Fibre Channel

Page 2

G52307-0, Rev 2.2

10/10/00

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Functional Description

Notation

In this document, each of the four channels are identified as Channel A, B, C or D. When discussing a sig-

nal on any specific channel, the signal will have the Channel letter embedded in the name, for example,

“TA[0:9]”. When referring to the common behavior of a signal which is used on each of the four channels, a

lower case “x” is used in the signal name, i.e. TXi[0:9]. Differential signals, such as RA+ and RA-, may be

referred to as a single signal, i.e. RA, by dropping reference to the “+” and “-”. “RFC” refers to either the TTL

input RFCT, or the PECL differential inputs RFC+/RFC-, whichever is used.

Clock Synthesizer

The VSC7182 clock synthesizer multiplies the reference frequency provided on the RFC input by 10 or 20

to achieve a baud rate clock between 1.05GHz and 1.36GHz. The RFC input can be either TTL or PECL. If

TTL, connect the TTL input clock to RFCT. If PECL, connect the PECL inputs to RFC+ and RFC-. The inter-

nal clock presented to the clock synthesizer is a logical XNOR of RFCT and RFC+/-. The reference clock will

be active HIGH if the unused input is HIGH. The reference clock is active LOW if the unused input is LOW.

RFCT has an internal pull-up resistor. Internal biasing resistors set the proper DC level on RFC+/- so AC-cou-

pling may be used.

The TTL outputs, RFCO0 and RFCO1, provide a clock that is frequency-locked to the RFC input. This

RFCM input.

The on-chip PLL uses a single external 0.1

µF capacitor, connected between CAP0 and CAP1, to control the

loop filter. This capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working voltage

rating and a good temperature coefficient (NPO is preferred but X7R may be acceptable). These capacitors are

used to minimize the impact of common-mode noise on the Clock Multiplier Unit (CMU), especially power

supply noise. Higher value capacitors provide better robustness in systems. NPO is preferred because if an X7R

capacitor is used, the power supply noise sensitivity will vary with temperature.

For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor

between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to ground,

C3. Larger values are better but 0.1

µF is adequate. However, if the designer cannot use a three capacitor

circuit, a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces.

Figure 1: Loop Filter Capacitors (Best Circuit)

CAP0

CAP1

C1

C2

C3

VSC7182

C1=C2=C3= >0.1

µF

MultiLayer Ceramic

Surface Mount

NPO (Preferred) or X7R

5V Working Voltage Rating