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CY62148G18-55ZSXI Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY62148G18-55ZSXI
Description  4-Mbit (512K words 횞 8 bit) Static RAM with Error-Correcting Code (ECC)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62148G18-55ZSXI Datasheet(HTML) 7 Page - Cypress Semiconductor

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Document Number: 001-95415 Rev. *E
Page 7 of 17
CY62148G MoBL®
Data Retention Characteristics
Over the Operating range
Parameter
Description
Conditions
Min
Typ [10]
Max
Unit
VDR
VCC for data retention
1
–
–
V
ICCDR[11, 12]
Data retention current
VCC = 1.2 V,
CE1 > VCC  0.2 V or CE2 < 0.2 V,
VIN > VCC  0.2 V or VIN < 0.2 V
––
13
A
tCDR[13, 14]
Chip deselect to data retention
time
0–
–
ns
tR[14]
Operation recovery time
45/55
–
–
ns
Data Retention Waveform
Figure 3. Data Retention Waveform
t CD R
t R
V DR  =  1. 0  V
DA T A   RE T E N T I O N   MO D E
V CC (m in )
V CC (m in )
V CC
CE
Notes
10. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC =3V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
11. Chip enables CE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
12. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
13. These parameters are guaranteed by design.
14. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.


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