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CY62167GN18-55BVXIT Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY62167GN18-55BVXIT Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 19 page  Document Number: 001-93628 Rev. *D Page 8 of 19 CY62167GN MoBL® Switching Characteristics Parameter[20] Description 45 ns 55 ns Unit Min Max Min Max Read Cycle tRC Read cycle time 45.0 – 55.0 – ns tAA Address to data valid – 45.0 – 55.0 ns tOHA Data hold from address change 10.0 – 10.0 – ns tACE CE1 LOW and CE2 HIGH to data valid – 45.0 – 55.0 ns tDOE OE LOW to data valid – 22.0 – 25.0 ns tLZOE OE LOW to Low Z [21, 22] 5.0 – 5.0 – ns tHZOE OE HIGH to High Z [21, 22, 23] – 18.0 – 18.0 ns tLZCE CE1 LOW and CE2 HIGH to Low Z [21, 22] 10.0 – 10.0 – ns tHZCE CE1 HIGH and CE2 LOW to High Z [21, 22, 23] – 18.0 – 18.0 ns tPU CE1 LOW and CE2 HIGH to power-up[24] 0 – 0 – ns tPD CE1 HIGH and CE2 LOW to power-down[24] – 45.0 – 55.0 ns tDBE BLE / BHE LOW to data valid – 45.0 – 55.0 ns tLZBE BLE / BHE LOW to Low Z [21, 22] 5.0 – 5.0 – ns tHZBE BLE / BHE HIGH to High Z [21, 22, 23] – 18.0 – 18.0 ns Write Cycle[25, 26] tWC Write cycle time 45 – 55 – ns tSCE CE1 LOW and CE2 HIGH to write end 35 – 40 – ns tAW Address setup to write end 35 – 40 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 35 – 40 – ns tBW BLE / BHE LOW to write end 35 – 40 – ns tSD Data setup to write end 25 – 25 – ns tHD Data hold from write end 0 – 0 – ns tHZWE WE LOW to High Z [21, 22, 23] – 18 – 20 ns tLZWE WE HIGH to Low Z [21, 22] 10 – 10 – ns Notes 20. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 3 on page 6. 21. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 22. Tested initially and after any design or process changes that may affect these parameters. 23. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 24. These parameters are guaranteed by design and are not tested. 25. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write 26. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tHZWE and tSD. |
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