PRELIMINARY

CY28412

Document #: 38-07612 Rev. *C

Page 8 of 17

Calculating Load Capacitors

In addition to the standard external trim capacitors, trace

capacitance and pin capacitance must also be considered to

correctly calculate crystal loading. As mentioned previously,

the capacitance on each side of the crystal is in series with the

crystal. This means the total capacitance on each side of the

crystal must be twice the specified crystal load capacitance

(CL). While the capacitance on each side of the crystal is in

series with the crystal, trim capacitors (Ce1,Ce2) should be

calculated to provide equal capacitive loading on both sides.

As mentioned previously, the capacitance on each side of the

crystal is in series with the crystal. This mean the total capac-

itance on each side of the crystal must be 2 times the specified

load capacitance (CL). While the capacitance on each side of

the crystal is in series with the crystal, trim capacitors

(Ce1,Ce2) should be calculated to provide equal capacitance

loading on both sides.

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

CL....................................................Crystal load capacitance

CLe......................................... Actual loading seen by crystal

using standard value trim capacitors

Ce..................................................... External trim capacitors

Cs ..............................................Stray capacitance (terraced)

Ci .......................................................... Internal capacitance

(lead frame, bond wires etc.)

PD (Power-down) Clarification

The VTT_PWRGD# /PD pin is a dual function pin. During initial

power-up, the pin functions as VTT_PWRGD#. Once

VTT_PWRGD# has been sampled low by the clock chip, the

pin assumes PD functionality. The PD pin is an asynchronous

active high input used to shut off all clocks cleanly prior to

shutting off power to the device. This signal is synchronized

internal to the device prior to powering down the clock synthe-

sizer. PD is also an asynchronous input for powering up the

system. When PD is asserted high, all clocks are driven to a

low value and held prior to turning off the VCOs and the crystal

oscillator.

PD (Power-down) – Assertion

When PD is sampled high by two consecutive rising edges of

CPUC, all single-ended outputs will be held low on their next

high to low transition and differential clocks must be held high

or Hi-Z (depending on the state of the control register drive

mode bit) on the next diff clock# high to low transition. When

the SMBus PD drive mode bit corresponding to the differential

Figure 1. Crystal Capacitive Clarification

XTAL

Ce2

Ce1

Cs1

Cs2

X1

X2

Ci1

Ci2

Clock Chip

Trace

2.8pF

Trim

33pF

Pin

3 to 6p

Figure 2. Crystal Loading Example

Load Capacitance (each side)

Total Capacitance (as seen by the crystal)

Ce = 2 * CL – (Cs + Ci)

Ce1 + Cs1 + Ci1

1

+

Ce2 + Cs2 + Ci2

1

(

)

1

=

CLe

[+] Feedback