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UCC21222QDRQ1 Datasheet(PDF) 3 Page - Texas Instruments |
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UCC21222QDRQ1 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 43 page  3 UCC21222-Q1 www.ti.com SLUSDA5 – FEBRUARY 2018 Product Folder Links: UCC21222-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) P = power, I = input, O = output 5 Pin Configuration and Functions D Package 16-Pin SOIC Top View Pin Functions PIN I/O (1) Description NAME NO. DIS 5 I Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. Bypass using a ≈ 1-nF low ESR/ESL capacitor close to DIS pin when connecting to a µC with distance. DT 6 I Programmable dead time function. Tying DT to VCCI or leaving DT open allows the outputs to overlap. Placing a resistor (RDT) between DT and GND adjusts dead time according to the equation: DT (in ns) = 10 × RDT (in kΩ). TI recommends bypassing this pin with a ceramic capacitor, 2.2 nF or greater, to achieve better noise immunity. Place this capacitor and RDT close to the DT pin. GND 4 P Primary-side ground reference. All signals in the primary side are referenced to this ground. INA 1 I Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. INB 2 I Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. NC 7 - No internal connection. 12 13 OUTA 15 O Output of driver A. Connect to the gate of the A channel FET or IGBT. OUTB 10 O Output of driver B. Connect to the gate of the B channel FET or IGBT. VCCI 3 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible. VCCI 8 P This pin is internally shorted to pin 3. VDDA 16 P Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located as close to the device as possible. VDDB 11 P Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located as close to the device as possible. VSSA 14 P Ground for secondary-side driver A. Ground reference for secondary side A channel. VSSB 9 P Ground for secondary-side driver B. Ground reference for secondary side B channel. |
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