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CY14E116N-Z45XI Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY14E116N-Z45XI
Description  16-Mbit (2048K8/1024K16/512K32) nvSRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14E116N-Z45XI Datasheet(HTML) 8 Page - Cypress Semiconductor

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CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
Document Number: 001-67793 Rev. *N
Page 8 of 37
Device Operation
The CY14X116L/CY14X116N/CY14X116S nvSRAM is made up
of two functional components paired in the same physical cell.
These are an SRAM memory cell and a nonvolatile
QuantumTrap cell. The SRAM memory cell operates as a
standard fast static RAM. Data in the SRAM is transferred to the
nonvolatile cell (the STORE operation) automatically at
power-down, or from the nonvolatile cell to the SRAM (the
RECALL operation) on power-up. Both the STORE and RECALL
operations are also available under software control. Using this
unique architecture, all cells are stored and recalled in parallel.
During the STORE and RECALL operations, SRAM read and
write operations are inhibited. The CY14X116L/CY14X116N/
CY14X116S supports infinite reads and writes to the SRAM. In
addition, it provides infinite RECALL operations from the nonvol-
atile cells and up to 1 million STORE operations. See the Truth
Table For SRAM Operations on page 24 for a complete
description of read and write modes.
SRAM Read
The CY14X116L/CY14X116N/CY14X116S performs a read
cycle whenever CE and OE are LOW, and WE, ZZ, and HSB are
HIGH. The address specified on pins A0–A20 or A0–A19 or
A0–A18 determines which of the 2,097,152 data bytes or
1,048,576 words of 16 bits or 524,288 words of 32 bits each are
accessed. Byte enables (BLE, BHE) determine which bytes are
enabled to the output, in the case of 16-bit words and byte
enables (BA, BB, BC, BD) determine which bytes are enabled to
the output, in the case of 32-bit words. When the read is initiated
by an address transition, the outputs are valid after a delay of tAA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins
DQ0–DQ31 is written into the memory if it is valid tSD before the
end of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BLE, BHE determine which bytes
are written, in the case of 16-bit words and Byte Enable inputs
(BA, BB, BC, BD) determine which bytes are written, in the case
of 32-bit words. Keep OE HIGH during the entire write cycle to
avoid data bus contention on the common I/O lines. If OE is left
LOW, the internal circuitry turns off the output buffers tHZWE after
WE goes LOW.
AutoStore Operation (Power-Down)
The CY14X116L/CY14X116N/CY14X116S stores data to the
nonvolatile QuantumTrap cells using one of the three storage
operations. These three operations are: Hardware STORE,
activated by the HSB; Software STORE, activated by an address
sequence; AutoStore, on device power-down. The AutoStore
operation is a unique feature of nvSRAM and is enabled by
default on the CY14X116L/CY14X116N/CY14X116S.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a STORE operation during
power-down. If the voltage on the VCC pin drops below VSWITCH,
the part automatically disconnects the VCAP pin from VCC and a
STORE operation is initiated with power provided by the VCAP
capacitor.
Note If the capacitor is not connected to the VCAP pin, AutoStore
must be disabled using the soft sequence specified in the section
Preventing AutoStore on page 12. If AutoStore is enabled without
a capacitor on the VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the STORE. This
corrupts the data stored in the nvSRAM.
Figure 8. AutoStore Mode
Figure 8 shows the proper connection of the storage capacitor
(VCAP) for the automatic STORE operation. Refer to DC
Electrical Characteristics on page 13 for the size of the VCAP. The
voltage on the VCAP pin is driven to VVCAP by a regulator on the
chip. A pull-up resistor should be placed on WE to hold it inactive
during power-up. This pull-up resistor is only effective if the WE
signal is in tristate during power-up. When the nvSRAM comes
out of power-up-RECALL, the host microcontroller must be
active or the WE held inactive until the host microcontroller
comes out of reset.
To reduce unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place (which sets a write latch) since
the most recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether a write
operation has taken place.
0.1 uF
VCC
VCAP
WE
VCAP
V
SS
V
CC


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