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CY14E116N-Z30XI Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY14E116N-Z30XI Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 37 page  CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Document Number: 001-67793 Rev. *N Page 9 of 37 Hardware STORE (HSB) Operation The CY14X116L/CY14X116N/CY14X116S provides the HSB pin to control and acknowledge the STORE operations. The HSB pin is used to request a Hardware STORE cycle. When the HSB pin is driven LOW, the device conditionally initiates a STORE operation after tDELAY. A STORE cycle begins only if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (an internal 100-k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by an internal 100-k pull-up resistor. SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. If the write latch is not set, HSB is not driven LOW by the device. However, any of the SRAM read and write cycles are inhibited until HSB is returned HIGH by the host microcon- troller or another external source. During any STORE operation, regardless of how it is initiated, the device continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after the HSB pin returns HIGH. Leave the HSB uncon- nected if it is not used. Hardware RECALL (Power-Up) During power-up or after any low-power condition (VCC <VSWITCH), an internal RECALL request is latched. When VCC again exceeds the VSWITCH on power-up, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. A Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle, the previous nonvolatile data is first erased, followed by a store into the nonvolatile elements. After a STORE cycle is initiated, further reads and writes are disabled until the cycle is completed. Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence. Otherwise, the sequence is aborted and no STORE or RECALL takes place. To initiate the Software STORE cycle, the following read sequence must be performed: 1. Read address 0x4E38 Valid Read 2. Read address 0xB1C7 Valid Read 3. Read address 0x83E0 Valid Read 4. Read address 0x7C1F Valid Read 5. Read address 0x703F Valid Read 6. Read address 0x8FC0 Initiate STORE cycle The software sequence may be clocked with CE-controlled reads or OE-controlled reads, with WE kept HIGH for all the six read sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, perform the following sequence of CE or OE controlled read operations: 1. Read address 0x4E38 Valid Read 2. Read address 0xB1C7 Valid Read 3. Read address 0x83E0 Valid Read 4. Read address 0x7C1F Valid Read 5. Read address 0x703F Valid Read 6. Read address 0x4C63 Initiate RECALL cycle Internally, RECALL is a two-step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements. |
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