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CY14B116L-Z30XIT Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY14B116L-Z30XIT Datasheet(HTML) 11 Page - Cypress Semiconductor |
11 / 37 page CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Document Number: 001-67793 Rev. *N Page 11 of 37 Table 1. Mode Selection CE[10] WE OE BLE, BHE / BA, BB, BC, BD[11] A15 - A0[12] Mode I/O Power H X X X X Not selected Output High Z Standby L H L L X Read SRAM Output Data Active L L X L X Write SRAM Input Data Active L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output Data Output Data Output Data Output Data Output Data Output Data Active[13] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Output Data Output Data Output Data Output Data Output Data Output Data Active[13] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z Active ICC2[13] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z Active[13] Notes 10. The TSOP II package is offered in single CE. TSOP I, and BGA packages are offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted on any of the chip enable pins (CE for the single chip enable device; CE1 and CE2 for the dual chip enable device). 11. BLE, BHE are applicable for the ×16 configuration and BA, BB, BC, BD are applicable for the ×32 configuration only. 12. While there are 21 address lines on the CY14X116L (20 address lines on the CY14X116N and 19 address lines on the CY14X116S), only 13 address lines (A14–A2) are used to control software modes. The remaining address lines are don’t care. 13. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile operation. |
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