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MC74LVX4052DR2 Datasheet(PDF) 8 Page - ON Semiconductor |
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MC74LVX4052DR2 Datasheet(HTML) 8 Page - ON Semiconductor |
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8 / 16 page 
MC74LVX4052 http://onsemi.com 8 Figure 10. Charge Injection, Test Set–Up ON/OFF 7 8 VCC VOUT OFF/ON 9–11 CL* VIH VIL *Includes all probe and jig capacitance. 16 Bias Channel Selects to test each combination of analog inputs to common analog output. 6 Enable VEE VIN RIS VIS VOUT DVOUT Q = CL * DVOUT Figure 11. Maximum On Channel Feedthrough On Loss, Test Set–Up OFF ON 6 7 8 VCC VEE 9–11 All untested Analog I/O pins HP11667B Pwr Splitter HP4195A Network Anl 0.1 mF S1 R1 T1 0.1 mF 50 W 100 K W VIS 16 Config = Network Format = T/R (dB) CAL = Trans Cal Display = Rectan X *A)B Scale Ref = Auto Scale View = Off, Off, Off Trig = Cont Mode Source Amplitude = )13 dB Reference Attenuation = 20 dB Test Attenuation = 20 dB VONL(dB) = 20 log (VT1/VR1) Channel Selects connected to address pins on HP4195A and appropriately configured to test each switch. |
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