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CY14E116S Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY14E116S Datasheet(HTML) 10 Page - Cypress Semiconductor |
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10 / 37 page  CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Document Number: 001-67793 Rev. *N Page 10 of 37 Sleep Mode In Sleep mode, the device consumes the lowest power supply current (IZZ). The device enters a low-power Sleep mode after asserting the ZZ pin LOW. After the Sleep mode is registered, the nvSRAM does a STORE operation to secure the data to the nonvolatile memory and then enters the low-power mode. The device starts consuming IZZ current after tSLEEP time from the instance when the sleep mode is initiated. When the ZZ pin is LOW, all input pins are ignored except the ZZ pin. The nvSRAM is not accessible for normal operations while it is in sleep mode. When the ZZ pin is de-asserted (HIGH), there is a delay tWAKE before the user can access the device. If sleep mode is not used, the ZZ pin should be tied to VCC. Note When nvSRAM enters sleep mode, it initiates a nonvolatile STORE cycle, which results in losing one endurance cycle for every Sleep mode entry unless data has not been written to the nvSRAM since the last nonvolatile STORE/RECALL operation. Note If the ZZ pin is LOW during power-up, the device will not be in Sleep mode. However, the I/Os are in tristate until the ZZ pin is de-asserted (HIGH). Figure 9. Sleep Mode (ZZ) Flow Diagram Device Ready Active Mode (ICC) Standby Mode (ISB) Sleep Routine Sleep Mode (IZZ) After tSLEEP CE = LOW; ZZ = HIGH CE = LOW CE = HIGH; ZZ = HIGH ZZ = LOW ZZ = LOW CE = Don’t Care ZZ = HIGH CE = HIGH ZZ = HIGH ZZ = HIGH Power Applied After tHRECALL After tWAKE |
Similar Part No. - CY14E116S |
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Similar Description - CY14E116S |
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