Electronic Components Datasheet Search |
|
CS43L36 Datasheet(PDF) 50 Page - Cirrus Logic |
|
CS43L36 Datasheet(HTML) 50 Page - Cirrus Logic |
50 / 89 page DS1081F3 50 CS43L36 5.2 Power-Down Sequence 5.2 Power-Down Sequence Ex. 5-2 is the procedure for powering down the HP playback. 4.16Disable the SRC bypass. Serial Port SRC Control. 0x1007 0x10 Reserved I2C_DRIVE Reserved SRC_BYPASS_DAC Reserved 0001 0 0 0 0 — I2C output drive strength normal — SRC not bypassed for DAC path — 5 Enable SCLK. ASP Clock Configuration 1. 0x1207 0x20 Reserved ASP_SCLK_EN ASP_HYBRID_MODE Reserved ASP_SCPOL_IN_DAC ASP_LCPOL_OUT ASP_LCPOL_IN 00 1 0 0 0 0 0 — ASP SCLK enabled. LRCK is an input generated from SCLK. — SCLK input drive polarity for DAC is normal. LRCK output drive polarity is normal. LRCK input polarity (pad to logic) is normal. 6 Configure the DAC. DAC Control 1. 0x1F01 0x00 Reserved DACB_INV DACA_INV 0000 00 0 0 — DACA signal not inverted. DACB signal not inverted. 7 Configure the appropriate volume controls and DAC source selects. 7.1 Set Mixer A input to 0 dB. Channel A Input Volume. 0x2301 0x00 Reserved CHA_VOL 00 00 0000 — Input A is set to 0 dB. 7.2 Set Mixer B input to 0 dB. Channel B Input Volume. 0x2303 0x00 Reserved CHB_VOL 00 00 0000 — Input B is set to 0 dB. 8 Configure the HP control.HP Control. 0x2001 0x03 Reserved ANA_MUTE_B ANA_MUTE_A FULL_SCALE_VOL Reserved 0000 0 0 1 1 — Channel B is unmuted. Channel A is unmuted. Full-scale volume is -6dB for headphone output. — 9 Power up the DAC/HP. Power Down Control 1. 0x1101 0x96 Reserved ASP_DAI_PDN MIXER_PDN Reserved HP_PDN Reserved PDN_ALL 1 0 0 1 0 11 0 — ASP input path is powered up. Mixer is powered up. — HPOUT powered up. — DAC powered up. 10 The headphone amplifier is operational after 10 ms. Example 5-2. Power-Down Sequence STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION 1 Configure the DAC/volume Channels. 1.1 Mute Volume A input. Channel A Input Volume. 0x2301 0x3F Reserved CHA_VOL 00 11 1111 — Input A is muted. 1.2 Mute Volume B input. Channel B Input Volume. 0x2303 0x3F Reserved CHB_VOL 00 11 1111 — Input B is muted. 1.3 Mute Channel A and B inputs. HP Control. 0x2001 0x0F Reserved ANA_MUTE_B ANA_MUTE_A FULL_SCALE_VOL Reserved 0000 1 1 1 1 — Channel B is muted. Channel A is muted. Full-scale volume is –6 dB for headphone output. — 1.4 Disable SCLK. ASP Clock Configuration 1. 0x1207 0x00 Reserved ASP_SCLK_EN ASP_HYBRID_MODE Reserved ASP_SCPOL_IN_DAC ASP_LCPOL_OUT ASP_LCPOL_IN 00 0 0 0 0 0 0 — ASP SCLK disabled. LRCK is an output generated from SCLK. — SCLK input drive polarity for DAC is normal. LRCK output drive polarity is normal. LRCK input polarity (pad to logic) is normal. Example 5-1. Power-Up Sequence (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
Similar Part No. - CS43L36 |
|
Similar Description - CS43L36 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |