CY7C25422KV18-333BZXI datasheet(8/28 Pages) CYPRESS

Part #	CY7C25422KV18-333BZXI

Description	72-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT

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Manufacturer	CYPRESS [Cypress Semiconductor]

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Document Number: 001-90368 Rev. *D

Page 8 of 28

CY7C25422KV18

On-Die Termination (ODT)

These devices have an On-Die Termination feature for Data

inputs (D[x:0]), Byte Write Selects (BWS[x:0]), and Input Clocks (K

and K). The termination resistors are integrated within the chip.

The ODT range selection is enabled through ball R6 (ODT pin).

The ODT termination tracks value of RQ where RQ is the resistor

tied to the ZQ pin. ODT range selection is made during power up

initialization. A LOW on this pin selects a low range that follows

RQ/3.33 for 175

< RQ < 350 (where RQ is the resistor tied

to ZQ pin)

A HIGH on this pin selects a high range that follows

RQ/1.66 for 175

< RQ < 250 (where RQ is the resistor tied

to ZQ pin). When left floating, a high range termination value is

selected by default. For a detailed description on the ODT

implementation, refer to the application note, On-Die Termination

for QDRII+/DDRII+ SRAMs.

PLL

These chips use a PLL that is designed to function between

120 MHz and the specified maximum clock frequency. During

power up, when the DOFF is tied HIGH, the PLL is locked after

20

s of stable clock. The PLL can also be reset by slowing or

stopping the input clocks K and K for a minimum of 30 ns.

However, it is not necessary to reset the PLL to lock to the

desired frequency. The PLL automatically locks 20

s after a

stable clock is presented. The PLL may be disabled by applying

ground to the DOFF pin. When the PLL is turned off, the device

behaves in QDR I mode with one cycle latency and a longer

access time). For information, refer to the application note, PLL

Considerations in QDRII/DDRII/QDRII+/DDRII+.

Application Example

Figure 2 shows two QDR II+ used in an application.

Figure 2. Application Example

D[x:0]

ARPS WPS BWS KK

Q[x:0]

ZQ

SRAM#1

CQ/CQ

D[x:0]

ARPS WPS BWS KK

Q[x:0]

ZQ

SRAM#2

CQ/CQ

DATA IN[2x:0]

DATA OUT [2x:0]

ADDRESS

RPS

WPS

BWS

CLKIN1/CLKIN1

CLKIN2/CLKIN2

SOURCE K

FPGA / ASIC

RQ

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