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CY7C4021KV13-600FCXC Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY7C4021KV13-600FCXC Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 46 page  CY7C4021KV13/CY7C4041KV13 Document Number: 001-79553 Rev. *O Page 9 of 46 Functional Overview The QDR-IV HP SRAM is a two word burst synchronous SRAM equipped with dual independent bidirectional data ports. The following sections describe the operation of QDR-IV HP SRAM. Clocking There are three groups of clock signals: CK/CK#, DKx/DKx#, and QKx/QKx#, where x can be A or B, referring to the respective ports. The CK/CK# clock is associated with the address and control pins: A[24:0], LDA#, LDB#, RWA#, RWB#. The CK/CK# transitions are centered with respect to the address and control signal transitions. The DKx/DKx# clocks are associated with write data. The DKx/DKx# clocks are used as source-centered clocks for the double data rate DQx and DINVx pins, when acting as inputs for the write data. The QKx/QKx# clocks are associated with read data. The QKx/QKx# clocks are used as source-synchronous clocks for the double data rate DQx and DINVx pins, when acting as outputs for the read data. Command Cycles The QDR-IV HP SRAM read and write commands are driven by the control inputs (LDA#, LDB#, RWA#, and RWB#) and the Address Bus. The port A control inputs (LDA# and RWA#) are sampled at the rising edge of the input clock. The port B control inputs (LDB# and RWB#) are sampled at the falling edge of the input clock. For port A: When LDA# = 0 and RWA# = 1, a read operation is initiated. When LDA# = 0 and RWA# = 0, a write operation is initiated. The address is sampled on the rising edge of the input clock. For port B: When LDB# = 0 and RWB# = 1, a read operation is initiated. When LDB# = 0 and RWB# = 0, a write operation is initiated. The address is sampled on the falling edge of the input clock. Read and Write Data Cycles Read data is supplied to the DQA pins exactly five clock cycles from the rising edge of the CK signal corresponding to the cycle where the read command was initiated. QVLDA is asserted one-half clock cycle prior to the first data word driven on the bus. It is de-asserted one-half cycle prior to the last data word driven on the bus. Data outputs are tri-stated in the clock following the last data word. Read data is supplied to the DQB pins exactly five clock cycles from the falling edge of the CK signal corresponding to the cycle that the read command was initiated. QVLDB is asserted one-half clock cycle prior to the first data word driven on the bus. It is de-asserted one-half cycle prior to the last data word driven on the bus. Data outputs are tri-stated in the clock following the last data word. Write data is supplied to the DQA pins exactly three clock cycles from the rising edge of the CK signal corresponding to the cycle where the write command was initiated. Write data is supplied to the DQB pins exactly three clock cycles from the falling edge of the CK signal corresponding to the cycle where the write command was initiated. Address and Data Bus Inversion To reduce simultaneous switching noise and I/O current, QDR-IV HP SRAM provides the ability to invert all address or data pins. The AINV pin indicates whether the address bus, A[24:0], and the address parity bit, AP, is inverted. The address bus and parity bit are considered one group. The function of the AINV is controlled by the memory controller. However, the following rules should be used in the system design. ■ For a × 36 configuration part, 20 address pins plus 1 parity bit are used for 21 signals in the address group. If the number of 0’s in the address group is>11, AINV is set to 1 by the controller. As a result, no more than 11 pins may switch in the same direction during each bit time. ■ For a × 18 data width part, 21 address pins plus 1 parity bit are used for 22 signals in the address group. If the number of 0’s in the address group is >12, AINV is set to 1 by the controller. As a result, no more f the number of 0’s in the address group than 12 pins may switch in the same direction during each bit time. The DINVA and DINVB pins indicate whether the corresponding DQA and DQB pins are inverted. ■ For a × 36 data width part, the data bus for each port is split into groups of 18 pins. Each 18-pin data group is guaranteed to be driving less than or equal to 10 pins low on any given cycle.If the number of 0s in the data group >10, DINV is set to 1. As a result, no more than 10 pins may switch in the same direction during each bit time. ■ For a × 18 data width part, the data bus for each port is split into groups of 9 pins. Each 9 pin data group is guaranteed to be driving less than or equal to 5 pins low on any given cycle. If the number of 0s in the data group is >5, DINV is set to 1 As a result, no more than 5 pins may switch in the same direction during each bit time. AINV, DINVA[1:0], DINVB[1:0] are all active high. When set to1, the corresponding bus is inverted. If the data inversion feature is programmed to be OFF, then the DINVA/DINVB output bits will always be driven to 0. These functions are programmable through the configuration registers and can be enabled or disabled for the address bus and the data bus independently. During configuration register read and write cycles, the address inversion input is ignored and the data inversion output is always driven to 0 when register read data is driven on the data bus. Specifically, the register read data is driven on DQA[7:0] and the DINVA[0] bit is driven to 0. All other DQA/DQB data bits and DINVA/DINVB bits are tri-stated. In addition, the address parity input (AP) is ignored. |
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