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CY7C2644KV18-333BZXI Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY7C2644KV18-333BZXI
Description  144-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C2644KV18-333BZXI Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY7C2642KV18/CY7C2644KV18
Document Number: 001-44138 Rev. *P
Page 6 of 30
Functional Overview
The CY7C2642KV18, and CY7C2644KV18 are synchronous
pipelined Burst SRAMs equipped with a read port and a write
port. The read port is dedicated to read operations and the write
port is dedicated to write operations. Data flows into the SRAM
through the write port and flows out through the read port. These
devices multiplex the address inputs to minimize the number of
address pins required. By having separate read and write ports,
the QDR II+ completely eliminates the need to “turn around” the
data bus and avoids any possible data contention, thereby
simplifying system design. Each access consists of two 18-bit
data transfers in the case of CY7C2642KV18, and two 36-bit
data transfers in the case of CY7C2644KV18 in one clock cycle.
These devices operate with a read latency of two cycles when
DOFF pin is tied high. When DOFF pin is set low or connected
to VSS then the device behaves in QDR I mode with a read
latency of one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input and output timing
are referenced from the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the input clocks (K and K) as well.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C2642KV18 is described in the following sections. The
same basic descriptions apply to CY7C2644KV18.
Read Operations
The CY7C2642KV18 is organized internally as two arrays of
4 M × 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. The address
K
Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0].
CQ
Echo Clock Synchronous echo clock outputs. This is a free-running clock and is synchronized to the input clock
(K) of the QDR II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.
CQ
Echo Clock Synchronous echo clock outputs. This is a free-running clock and is synchronized to the input clock
(K) of the QDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23.
ZQ
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL turn off
 Active low. Connecting this pin to ground turns off the PLL inside the device. The timing
in the operation with the PLL turned off differs from those listed in this data sheet. For normal operation,
connect this pin to a pull up through a 10 K
 or less pull up resistor. The device behaves in QDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR I timing.
TDO
Output
Test data-out (TDO) pin for JTAG.
TCK
Input
Test clock (TCK) pin for JTAG.
TDI
Input
Test data-in (TDI) pin for JTAG.
TMS
Input
Test mode select (TMS) pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
Input
Not connected to the die. Can be tied to any voltage level.
VREF
Input-
Reference
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name
I/O
Pin Description


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