CY7C2268KV18/CY7C2270KV18

Document Number: 001-57845 Rev. *I

Page 6 of 31

Functional Overview

The CY7C2268KV18, and CY7C2270KV18 are synchronous

pipelined burst SRAMs equipped with a DDR interface, which

operates with a read latency of two and half cycles when DOFF

pin is tied HIGH. When DOFF pin is set LOW or connected to

one clock cycle.

Accesses are initiated on the rising edge of the positive input

clock (K). All synchronous input and output timing is referenced

from the rising edge of the input clocks (K and K).

controlled by the rising edge of the input clocks (K and K). All

controlled by the rising edge of the input clocks (K and K).

input registers controlled by the rising edge of the input clock (K).

CY7C2268KV18 is described in the following sections. The

same basic descriptions apply to CY7C2270KV18.

Read Operations

The CY7C2268KV18 is organized internally as two arrays of

1M × 18. Accesses are completed in a burst of 2 sequential

18-bit data words. Read operations are initiated by asserting

R/W HIGH and LD LOW at the rising edge of the positive input

clock (K). The address presented to the address inputs is stored

in the read address register. Following the next two K clock rise,

the corresponding 18-bit word of data from this address location

On the subsequent rising edge of K, the next 18-bit data word is

the rising edge of the input clock (K and K). To maintain the

internal logic, each read access must be allowed to complete.

Read accesses can be initiated on every rising edge of the

positive input clock (K).

When read access is deselected, the CY7C2268KV18 first

completes the pending read transactions. Synchronous internal

circuitry automatically tri-states the output following the next

rising edge of the negative input clock (K). This enables for a

transition between devices without the insertion of wait states in

a depth expanded memory.

Write Operations

Write operations are initiated by asserting R/W LOW and LD

LOW at the rising edge of the positive input clock (K). The

address presented to address inputs is stored in the write

address register. On the following K clock rise, the data

subsequent rising edge of the negative input clock (K) the

of data are then written into the memory array at the specified

location. Write accesses can be initiated on every rising edge of

the positive input clock (K). Doing so pipelines the data flow such

that 18 bits of data can be transferred into the device on every

rising edge of the input clocks (K and K).

When the write access is deselected, the device ignores all

inputs after the pending write operations are completed.

Byte Write Operations

Byte write operations are supported by the CY7C2268KV18. A

write operation is initiated as described in the section Write

Operations on page 6. The bytes that are written are determined

DOFF

Input

PLL turn off

 active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin

can be connected to a pull up through a 10 k

 or less pull-up resistor. The device behaves in DDR I

mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to

167 MHz with DDR I timing.

TDO

Output

TDO pin for JTAG.

TCK

Input

TCK pin for JTAG.

TDI

Input

TDI pin for JTAG.

TMS

Input

TMS pin for JTAG.

NC

N/A

Not connected to the die. Can be tied to any voltage level.

NC/72M

Input

Not connected to the die. Can be tied to any voltage level.

NC/144M

Input

Not connected to the die. Can be tied to any voltage level.

NC/288M

Input

Not connected to the die. Can be tied to any voltage level.

Input-

reference

Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC

measurement points.

Power supply Power supply inputs to the core of the device.

Ground

Ground for the device.

Power supply Power supply inputs for the outputs of the device.

Pin Name

I/O

Pin Description