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CY7C2268KV18-550BZC Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY7C2268KV18-550BZC Datasheet(HTML) 7 Page - Cypress Semiconductor |
7 / 31 page CY7C2268KV18/CY7C2270KV18 Document Number: 001-57845 Rev. *I Page 7 of 31 by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate byte write select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation. DDR Operation The CY7C2268KV18 enables high performance operation through high clock frequencies (achieved through pipelining) and DDR mode of operation. The CY7C2268KV18 requires two No Operation (NOP) cycle during transition from a read to a write cycle. At higher frequencies, some applications require third NOP cycle to avoid contention. If a read occurs after a write cycle, address and data for the write are stored in registers. The write information is stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a posted write. If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers. Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5 × the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 and 350 , with VDDQ =1.5 V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the DDR II+ to simplify data capture on high speed systems. Two echo clocks are generated by the DDR II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free-running clocks and are synchronized to the input clock of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23. Valid Data Indicator (QVLD) QVLD is provided on the DDR II+ to simplify data capture on high speed systems. The QVLD is generated by the DDR II+ device along with data output. This signal is also edge aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives. On-Die Termination (ODT) These devices have an on-die termination feature for data inputs (D[x:0]), byte write selects (BWS[x:0]), and input clocks (K and K). The termination resistors are integrated within the chip. The ODT range selection is enabled through ball R6 (ODT pin). The ODT termination tracks value of RQ where RQ is the resistor tied to the ZQ pin. ODT range selection is made during power-up initialization. A LOW on this pin selects a low range that follows RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied to ZQ pin) A HIGH on this pin selects a high range that follows RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied to ZQ pin). When left floating, a high range termination value is selected by default. For a detailed description on the ODT implementation, refer to the application note, On-Die Termination for QDRII+/DDRII+ SRAMs. PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 20 s of stable clock. The PLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in DDR I mode (with one cycle latency and a longer access time). For information, refer to the application note, PLL Considerations in QDRII/DDRII/QDRII+/DDRII+. |
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