6 / 10 page
CY62157DV18
MoBL2
Document #: 38-05126 Rev. *B
Page 6 of 10
Read Cycle No. 2 (OE Controlled)[15, 16]
Write Cycle No. 1 (WE Controlled) [13, 17, 18, 19]
Notes:
16. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
17. Data I/O is high-impedance if OE = VIH.
18. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
50%
50%
DATA VALID
t
t
t
t
t
t
HIGH IMPEDANCE
t
t
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
VCC
SUPPLY
CURRENT
t
BHE
/BLE
t
t
DATA OUT
t
RC
ACE
PD
HZCE
HZBE
HZOE
LZBE
DOE
LZOE
LZCE
DBE
PU
t
t
t
t
t
t
t
t
t
DATA
IN
VALID
CE1
ADDRESS
CE2
WE
DATA I/O
OE
BHE /BLE
t
DON’T CARE
WC
SCE
SA
AW
PWE
HA
BW
HD
SD
HZOE
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
