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BT8375 Datasheet(PDF) 25 Page - Synaptics Incorporated. |
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BT8375 Datasheet(HTML) 25 Page - Synaptics Incorporated. |
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25 / 323 page  Bt8370/8375/8376 1.0 Pin Descriptions Fully Integrated T1/E1 Framer and Line Interface 1.1 Pin Assignments N8370DSE Conexant 1-9 Receive System Bus (RSB) RSBCKI RSB Clock Input I Bit clock and I/O signal timing for RSB according to system bus mode (see [SBI_CR; addr 0D0]). System chooses from 1 of four different clocks to act as RSB clock source (see [CMUX; addr 01A]). Rising or falling edge clocks are independently configurable for data signals RPCMO, RSIGO, RINDO and sync signals RFSYNC, RMSYNC (see [RPCM_NEG and RSYN_NEG; addr 0D1]). When configured to operate at twice the data rate, RSB clock is internally divided by 2 before clocking RSB data signals. RPCMO RSB Data Output O Serial data formatted into RSB frames consisting of DS0 channel time slots, optional F-bits, and optional ABCD signaling. Time slots are routed through receive slip buffer (see [RSLIPn; addr 1C0–1FF]) according to RSLIP mode (see [RSBI; addr 0D1]). Data for each output time slot is assigned sequentially from received time slot data according to system bus channel programming (see [ASSIGN; addr 0E0–0FF]). F-bits are output at the start of each RSB frame or at the embedded time slot location (see [EMBED; addr 0D0]). ABCD signaling is optionally inserted on a per-channel basis (see [INSERT; addr 0E0–0FF]) from the local signaling buffer (see [RLOCAL; addr 180–19F]) or from the receive signaling buffer [RSIGn; addr 1A0–1BF]. When enabled, robbed bit signaling or CAS reinsertion is performed according to T1/E1 mode: the eighth time slot bit of every sixth T1 frame is replaced, or the 4-bit signaling value in the E1 time slot 16 is replaced. RSIGO RSB Signaling Output O Serial data formatted into RSB frames consisting of ABCD signaling bits for each system bus time slot. Four bits of RSIGO time slot carry signaling state for each accompanying RPCMO time slot. Local or through signaling bits are output in every frame for each time slot and updated once per RSB multiframe, regardless of per-channel RPCMO signaling reinsertion. RINDO RSB Time Slot Indicator O Active-high output pulse marks selective receive system bus time slots as programmed by SBCn [addr 0E0–0FF]. RINDO occurs on RSBCKI rising or falling edges as selected by RPCM_NEG (see [RSBI; addr 0D1]). RFSYNC RSB Frame Sync PIO Input or output RSB frame sync (see [RFSYNC_IO; addr 018]). RFSYNC output is active-high for 1 RSB clock cycle at programmed offset bit location (see [RSYNC_BIT; addr 0D2]), marking offset bit within each RSB frame and repeating once every 125 µs. RSB timebase and RFSYNC output frame alignment begins at an arbitrary position and changes alignment according to RSLIP mode (see [RSBI; addr 0D1]). When RFSYNC is programmed as an input, the low-to-high signal transition is detected and aligns RSB timebase to the programmed offset. RSB timebase flywheels at 125 µs frame interval after the last RFSYNC is applied. RMSYNC RSB Multiframe Sync PIO Input or output RSB multiframe sync (see [RMSYNC_IO; addr 018]). RMSYNC output is active-high for 1 RSB clock cycle at programmed offset bit location (see [RSYNC_BIT; addr 0D2]), marking offset bit within each RSB multiframe and repeating once every 6 ms coinciding with RFSYNC. RSB timebase and RMSYNC output multiframe alignment begins at an arbitrary position and changes alignment according to RSLIP mode (see [RSBI; addr 0D1]). When RMSYNC is programmed as input, the low-to-high signal transition is detected and aligns the RSB timebase to the programmed offset and the first frame of the multiframe. RSB timebase flywheels at 6 ms multiframe interval after the last RMSYNC is applied. Table 1-1. Hardware Signal Definitions (6 of 8) Pin Label Signal Name I/O Definition |
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