CY7C1668KV18-450BZXC datasheet(7/30 Pages) CYPRESS

Part #	CY7C1668KV18-450BZXC

Description	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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Document Number: 001-44062 Rev. *K

Page 7 of 30

CY7C1668KV18

CY7C1670KV18

cycle. At higher frequencies, some applications require third

NOP cycle to avoid contention.

If a read occurs after a write cycle, address and data for the write

are stored in registers. The write information is stored because

the SRAM cannot perform the last word write to the array without

conflicting with the read. The data stays in this register until the

next write cycle occurs. On the first write cycle after the read(s),

the stored data from the earlier write is written into the SRAM

array. This is called a Posted write.

If a read is performed on the same address as the write, in the

previous cycle, the SRAM reads out the most current data. The

SRAM does this by bypassing the memory array and reading the

data from the registers.

Depth Expansion

Depth expansion requires replicating the LD control signal for

each bank. All other control signals can be common between

banks as appropriate.

Programmable Impedance

Connect an external resistor, RQ, between the ZQ pin on the

SRAM and VSS to enable the SRAM to adjust its output driver

impedance. The value of RQ must be 5 times the value of the

intended line impedance driven by the SRAM. The allowable

range of RQ to guarantee impedance matching with a tolerance

of ±15 percent is between 175

 and 350 , with VDDQ =1.5 V.

The output impedance is adjusted every 1024 cycles upon power

up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the DDR II+ to simplify data capture

on high speed systems. Two echo clocks are generated by the

DDR II+. CQ is referenced with respect to K and CQ is

referenced with respect to K. These are free-running clocks and

are synchronized to the input clock of the DDR II+. The timing for

the echo clocks is shown in the Switching Characteristics on

page 22.

Valid Data Indicator (QVLD)

QVLD is provided on the DDR II+ to simplify data capture on high

speed systems. The QVLD is generated by the DDR II+ device

along with data output. This signal is also edge aligned with the

echo clock and follows the timing of any data pin. This signal is

asserted half a cycle before valid data arrives.

PLL

These chips use a PLL that is designed to function between

120 MHz and the specified maximum clock frequency. During

power up, when the DOFF is tied HIGH, the PLL is locked after

20

s of stable clock. The PLL can also be reset by slowing or

stopping the input clock K and K for a minimum of 30 ns.

However, it is not necessary to reset the PLL to lock to the

desired frequency. The PLL automatically locks 20

s after a

stable clock is presented. The PLL may be disabled by applying

ground to the DOFF pin. When the PLL is turned off, the device

behaves in DDR I mode (with one cycle latency and a longer

access time).

Application Example

Figure 2 shows two DDR II+ used in an application.

Figure 2. Application Example (Width Expansion)

DQ[x:0]

ALD

R/W

BWS KK

ZQ

SRAM#1

CQ/CQ

DQ[x:0]

ALD

BWS KK

ZQ

SRAM#2

CQ/CQ

DQ[2x:0]

ADDRESS

BWS

CLKIN1/CLKIN1

CLKIN2/CLKIN2

SOURCE K

FPGA / ASIC

RQ

R/W

LD

R/W

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