CY7C1665KV18-550BZXC datasheet(2/31 Pages) CYPRESS

Part #	CY7C1665KV18-550BZXC

Description	144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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2 / 31 page

Document Number: 001-44060 Rev. *O

Page 2 of 31

CY7C1663KV18/CY7C1665KV18

Logic Block Diagram – CY7C1663KV18

Logic Block Diagram – CY7C1665KV18

CLK

A(20:0)

Gen.

K

Control

Logic

Address

Register

D[17:0]

Read Data Reg.

RPS

WPS

Control

Logic

Address

Register

Reg.

36

21

72

18

BWS[1:0]

VREF

Write

Reg

36

A(20:0)

21

18

CQ

DOFF

Q[17:0]

QVLD

18

Write

Reg

Write

Reg

Write

Reg

18

CLK

A(19:0)

Gen.

K

Control

Logic

Address

Register

D[35:0]

Read Data Reg.

RPS

WPS

Control

Logic

Address

Register

Reg.

72

20

144

36

BWS[3:0]

VREF

Write

Reg

72

A(19:0)

20

36

CQ

DOFF

Q[35:0]

QVLD

36

Write

Reg

Write

Reg

Write

Reg

36

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CY7C1665KV18-550BZXC Datasheet(PDF) 2 Page - Cypress Semiconductor

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