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CY7C1650KV18-450BZC Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY7C1650KV18-450BZC
Description  144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1650KV18-450BZC Datasheet(HTML) 6 Page - Cypress Semiconductor

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Document Number: 001-44061 Rev. *L
Page 6 of 29
CY7C1648KV18
CY7C1650KV18
Functional Overview
The CY7C1648KV18, and CY7C1650KV18 are synchronous
pipelined burst SRAMs equipped with a DDR interface, which
operates with a read latency of two cycles when DOFF pin is tied
high. When DOFF pin is set low or connected to VSS the device
behaves in DDR I mode with a read latency of one clock cycle.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input and output timing is referenced
from the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the input clocks (K and K).
All synchronous control (R/W, LD, BWS[X:0]) inputs pass through
input registers controlled by the rising edge of the input clock (K).
CY7C1648KV18 is described in the following sections. The
same basic descriptions apply to CY7C1650KV18.
Read Operations
The CY7C1648KV18 is organized internally as two arrays of
4 M × 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W high and LD low at the rising edge of the positive input clock
(K). The address presented to the address inputs is stored in the
read address register. Following the next two K clock rise, the
corresponding 18-bit word of data from this address location is
driven onto the Q[17:0] using K as the output timing reference. On
the subsequent rising edge of K, the next 18-bit data word is
driven onto the Q[17:0]. The requested data is valid 0.45 ns from
the rising edge of the input clock (K and K). To maintain the
internal logic, each read access must be allowed to complete.
Read accesses can be initiated on every rising edge of the
positive input clock (K).
When read access is deselected, the CY7C1648KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the output following the next rising
edge of the positive input clock (K). This enables a transition
between devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting R/W low and LD low
at the rising edge of the positive input clock (K). The address
presented to address inputs is stored in the write address
register. On the following K clock rise, the data presented to
D[17:0] is latched and stored into the 18-bit write data register,
provided BWS[1:0] are both asserted active. On the subsequent
rising edge of the negative input clock (K) the information
presented to D[17:0] is also stored into the write data register,
provided BWS[1:0] are both asserted active. The 36 bits of data
are then written into the memory array at the specified location.
Write accesses can be initiated on every rising edge of the
positive input clock (K). The data flow is pipelined such that 18
bits of data can be transferred into the device on every rising
edge of the input clocks (K and K).
When the write access is deselected, the device ignores all
inputs after the pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C1648KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature is used to simplify,
read, modify, or write operations to a byte write operation.
DDR Operation
The CY7C1648KV18 enables high performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1648KV18 requires two No
Operation (NOP) cycle during transition from a read to a write
cycle. At higher frequencies, some applications require a third
NOP cycle to avoid contention.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a Posted write.
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
NC/288M
Input
Not connected to the die. Can be tied to any voltage level.
VREF
Input-
Reference
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name
I/O
Pin Description


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