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CY7C1460KV25-167BZXI Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY7C1460KV25-167BZXI Datasheet(HTML) 8 Page - Cypress Semiconductor |
8 / 32 page Document Number: 001-66679 Rev. *J Page 8 of 32 CY7C1460KV25/CY7C1462KV25 CY7C1460KVE25/CY7C1462KVE25 Pin Definitions Pin Name I/O Type Pin Description A0, A1, A Input-synchronous Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK. BWa, BWb, BWc, BWd Input-synchronous Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd WE Input-synchronous Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD Input-synchronous Advance/load input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK Input-clock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 Input-synchronous Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE2 Input-synchronous Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 Input-synchronous Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE Input-asynchronous Output enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN Input-synchronous Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQa, DQb, DQc, DQd I/O-synchronous Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by AX during the previous read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tristate condition. The outputs are automatically tristated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPa, DQPb, DQPc, DQPd I/O-synchronous Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh. MODE Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. TDO JTAG serial output synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. |
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