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CY7C1648KV18 Datasheet(PDF) 22 Page - Cypress Semiconductor |
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CY7C1648KV18 Datasheet(HTML) 22 Page - Cypress Semiconductor |
22 / 29 page Document Number: 001-44061 Rev. *L Page 22 of 29 CY7C1648KV18 CY7C1650KV18 Switching Characteristics Over the Operating Range Parameters [29, 30] Description 450 MHz 400 MHz Unit Cypress Parameter Consortium Parameter Min Max Min Max tPOWER VDD(typical) to the first access [31] 1 – 1 – ms tCYC tKHKH K clock cycle time 2.20 8.4 2.50 8.4 ns tKH tKHKL Input clock (K/K) high 0.4 – 0.4 – tCYC tKL tKLKH Input clock (K/K) low 0.4 – 0.4 – tCYC tKHKH tKHKH K clock rise to K clock rise (rising edge to rising edge) 0.94 – 1.06 – ns Setup Times tSA tAVKH Address setup to K clock rise 0.275 – 0.4 – ns tSC tIVKH Control setup to K clock rise (LD, R/W) 0.275 – 0.4 – ns tSCDDR tIVKH Double data rate control setup to clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) 0.22 – 0.28 – ns tSD tDVKH D[X:0] setup to clock (K/K) rise 0.22 – 0.28 – ns Hold Times tHA tKHAX Address hold after K clock rise 0.275 – 0.4 – ns tHC tKHIX Control hold after K clock rise (LD, R/W) 0.275 – 0.4 – ns tHCDDR tKHIX Double data rate control hold after clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) 0.22 – 0.28 – ns tHD tKHDX D[X:0] hold after clock (K/K) rise 0.22 – 0.28 – ns Output Times tCO tCHQV K/K clock rise to data valid – 0.45 – 0.45 ns tDOH tCHQX Data output hold after output K/K clock rise (active to active) –0.45 – –0.45 – ns tCCQO tCHCQV K/K clock rise to echo clock valid – 0.45 – 0.45 ns tCQOH tCHCQX Echo clock hold after K/K clock rise –0.45 – –0.45 – ns tCQD tCQHQV Echo clock high to data valid – 0.15 – 0.20 ns tCQDOH tCQHQX Echo clock high to data invalid –0.15 – –0.20 – ns tCQH tCQHCQL Output clock (CQ/CQ) high [32] 0.85 – 1.00 – ns tCQHCQH tCQHCQH CQ clock rise to CQ clock rise (rising edge to rising edge) [32] 0.85 – 1.00 – ns tCHZ tCHQZ Clock (K/K) rise to high Z (active to high Z) [33, 34] – 0.45 – 0.45 ns tCLZ tCHQX1 Clock (K/K) rise to low Z [33, 34] –0.45 – –0.45 – ns tQVLD tCQHQVLD Echo clock high to QVLD valid [35] –0.15 0.15 –0.20 0.20 ns PLL Timing tKC Var tKC Var Clock phase jitter – 0.15 – 0.20 ns tKC lock tKC lock PLL lock time (K) 20 – 20 – s tKC Reset tKC Reset K static to PLL reset [36] 30 – 30 – ns Notes 29. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, VREF = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5 on page 21. 30. When a part with a maximum frequency above 333 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 31. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD min initially before a read or write operation can be initiated. 32. These parameters are extrapolated from the input timing parameters (tCYC/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production. 33. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 21. Transition is measured 100 mV from steady-state voltage. 34. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 35. tQVLD specification is applicable for both rising and falling edges of QVLD signal. 36. Hold to >VIH or <VIL. |
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