Document Number: 001-66680 Rev. *L

Page 8 of 31

CY7C1460KV33

CY7C1460KVE33

CY7C1462KVE33

Functional Overview

The

CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33

devices are synchronous-pipelined burst NoBL SRAMs designed

specifically to eliminate wait states during write/read transitions.

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with the

clock enable input signal (CEN). If CEN is HIGH, the clock signal

is not recognized and all internal states are maintained. All

synchronous operations are qualified with CEN. All data outputs

pass through output registers controlled by the rising edge of the

(250-MHz device).

Accesses can be initiated by asserting all three chip enables

enable (CEN) is active LOW and ADV/LD is asserted LOW, the

address presented to the device is latched. The access can

either be a read or write operation, depending on the status of

operations.

Write operations are qualified by the write enable (WE). All writes

are simplified with on-chip synchronous self timed write circuitry.

asynchronous output enable (OE) simplify depth expansion. All

operations (reads, writes, and deselects) are pipelined. ADV/LD

should be driven LOW after the device has been deselected to

load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise:

The address presented to the address inputs is latched into the

address register and presented to the memory core and control

logic. The control logic determines that a read access is in

progress and allows the requested data to propagate to the input

of the output register. At the rising edge of the next clock, the

requested data is allowed to propagate through the output

register and on to the data bus within 2.5 ns (250-MHz device)

provided OE is active LOW. After the first clock of the read

access, the output buffers are controlled by OE and the internal

control logic. OE must be driven LOW for the device to drive out

the requested data. During the second clock, a subsequent

operation (read/write/deselect) can be initiated. Deselecting the

device is also pipelined. Therefore, when the SRAM is

deselected at clock rise by one of the chip enable signals, its

output tristates following the next clock rise.

Burst Read Accesses

The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 have

an on-chip burst counter that enables the user the ability to

supply a single address and conduct up to four reads without

reasserting the address inputs. ADV/LD must be driven LOW to

load a new address into the SRAM, as described in the Single

Read Accesses section earlier. The sequence of the burst

counter is determined by the MODE input signal. A LOW input

on MODE selects a linear burst mode, a HIGH selects an

interleaved burst sequence. Both burst counters use A0 and A1

in the burst sequence, and wrap around when incremented

sufficiently. A HIGH input on ADV/LD increments the internal

burst counter regardless of the state of chip enables inputs or

WE. WE is latched at the beginning of a burst cycle. Therefore,

the type of access (read or write) is maintained throughout the

burst sequence.

Power supply

Power supply inputs to the core of the device.

I/O power supply

Power supply for the I/O circuitry.

Ground

Ground for the device. Should be connected to ground of the system.

NC

N/A

No connects. This pin is not connected to the die.

NC/72M

N/A

Not connected to the die. Can be tied to any voltage level.

NC/144M

N/A

Not connected to the die. Can be tied to any voltage level.

NC/288M

N/A

Not connected to the die. Can be tied to any voltage level.

NC/576M

N/A

Not connected to the die. Can be tied to any voltage level.

NC/1G

N/A

Not connected to the die. Can be tied to any voltage level.

ZZ

Input-asynchronous ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep”

condition with data integrity preserved. During normal operation, this pin can be connected to

Pin Name

I/O Type

Pin Description