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CY7C1460KV33 Datasheet(PDF) 23 Page - Cypress Semiconductor

Part No. CY7C1460KV33
Description  36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C1460KV33 Datasheet(HTML) 23 Page - Cypress Semiconductor

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Document Number: 001-66680 Rev. *L
Page 23 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Switching Characteristics
Over the Operating Range
Parameter [20, 21]
Description
–250
–200
–167
Unit
Min
Max
Min
Max
Min
Max
tPower[22]
VCC (typical) to the first access read or write
1
1
1
ms
Clock
tCYC
Clock cycle time
4.0
5.0
6.0
ns
FMAX
Maximum operating frequency
250
200
167
MHz
tCH
Clock HIGH
1.5
2.0
2.4
ns
tCL
Clock LOW
1.5
2.0
2.4
ns
Output Times
tCO
Data output valid after CLK rise
2.5
3.2
3.4
ns
tEOV
OE LOW to output valid
2.6
3.0
3.4
ns
tDOH
Data output hold after CLK rise
1.0
1.5
1.5
ns
tCHZ
Clock to high Z[23, 24, 25]
2.6
3.0
3.4
ns
tCLZ
Clock to low Z[23, 24, 25]
1.0
1.3
1.5
ns
tEOHZ
OE HIGH to output high Z[23, 24, 25]
2.6
3.0
3.4
ns
tEOLZ
OE LOW to output low Z[23, 24, 25]
0
0
0
ns
Setup Times
tAS
Address setup before CLK rise
1.2
1.4
1.5
ns
tDS
Data input setup before CLK rise
1.2
1.4
1.5
ns
tCENS
CEN setup before CLK rise
1.2
1.4
1.5
ns
tWES
WE, BWx setup before CLK rise
1.2
1.4
1.5
ns
tALS
ADV/LD setup before CLK rise
1.2
1.4
1.5
ns
tCES
Chip select setup
1.2
1.4
1.5
ns
Hold Times
tAH
Address hold after CLK rise
0.3
0.4
0.5
ns
tDH
Data input hold after CLK rise
0.3
0.4
0.5
ns
tCENH
CEN hold after CLK rise
0.3
0.4
0.5
ns
tWEH
WE, BWx hold after CLK rise
0.3
0.4
0.5
ns
tALH
ADV/LD hold after CLK rise
0.3
0.4
0.5
ns
tCEH
Chip select hold after CLK rise
0.3
0.4
0.5
ns
Notes
20. Timing reference is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
21. Test conditions shown in (a) of Figure 3 on page 22 unless otherwise noted.
22. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated.
23. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 3 on page 22. Transition is measured ± 200 mV from steady-state voltage.
24. At any voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high
Z prior to low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.


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