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CY7C1460KV33 Datasheet(PDF) 21 Page - Cypress Semiconductor

Part No. CY7C1460KV33
Description  36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C1460KV33 Datasheet(HTML) 21 Page - Cypress Semiconductor

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Document Number: 001-66680 Rev. *L
Page 21 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
IX
Input leakage current except ZZ
and MODE
GND
 VI  VDDQ
-5
5
A
Input current of MODE
Input = VSS
–30
A
Input = VDD
–5
A
Input current of ZZ
Input = VSS
–5
A
Input = VDD
–30
A
IOZ
Output leakage current
GND
 VI  VDDQ, output disabled
-5
5
A
IDD
VDD operating supply
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
220
mA
× 36
240
5-ns cycle,
200 MHz
× 18
190
mA
× 36
210
6-ns cycle,
167 MHz
× 18
170
mA
× 36
190
ISB1
Automatic CE power-down
current – TTL inputs
Max VDD,
device deselected,
VIN  VIH or VIN  VIL,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
85
mA
× 36
90
5-ns cycle,
200 MHz
× 18
85
mA
× 36
90
6-ns cycle,
167 MHz
× 18
85
mA
× 36
90
ISB2
Automatic CE power-down
current – CMOS inputs
Max VDD,
device deselected,
VIN  0.3 V or
VIN > VDDQ 0.3 V,
f = 0
All speed
grades
× 18
75
mA
× 36
80
ISB3
Automatic CE power-down
current – CMOS inputs
Max VDD, device
deselected,
VIN  0.3 V or
VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
85
mA
× 36
90
5-ns cycle,
200 MHz
× 18
85
× 36
90
mA
6-ns cycle,
167 MHz
× 18
85
× 36
90
mA
ISB4
Automatic CE power-down
current – TTL inputs
Max VDD, device
deselected,
VIN  VIH or VIN  VIL,
f = 0
All speed
grades
× 18
75
mA
× 36
80
Electrical Characteristics (continued)
Over the Operating Range
Parameter [17, 18]
Description
Test Conditions
Min
Max
Unit


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